From 368ab718d68453e029711f44935ee323b6efd452 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 26 Jul 2018 11:26:47 -0700 Subject: [PATCH] Change internal nets of 6T cell and write driver to have useful names for debugging. --- technology/freepdk45/sp_lib/cell_6t.sp | 12 ++++----- technology/scn3me_subm/sp_lib/cell_6t.sp | 12 ++++----- technology/scn3me_subm/sp_lib/write_driver.sp | 26 +++++++++---------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/technology/freepdk45/sp_lib/cell_6t.sp b/technology/freepdk45/sp_lib/cell_6t.sp index 6b1be024..cb9cbc3c 100644 --- a/technology/freepdk45/sp_lib/cell_6t.sp +++ b/technology/freepdk45/sp_lib/cell_6t.sp @@ -1,10 +1,10 @@ .SUBCKT cell_6t bl br wl vdd gnd -MM3 bl wl net10 gnd NMOS_VTG W=135.00n L=50n -MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n -MM1 net10 net4 gnd gnd NMOS_VTG W=205.00n L=50n -MM0 net4 net10 gnd gnd NMOS_VTG W=205.00n L=50n -MM5 net10 net4 vdd vdd PMOS_VTG W=90n L=50n -MM4 net4 net10 vdd vdd PMOS_VTG W=90n L=50n +MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n +MM2 br wl Qb gnd NMOS_VTG W=135.00n L=50n +MM1 Q Qb gnd gnd NMOS_VTG W=205.00n L=50n +MM0 Qb Q gnd gnd NMOS_VTG W=205.00n L=50n +MM5 Q Qb vdd vdd PMOS_VTG W=90n L=50n +MM4 Qb Q vdd vdd PMOS_VTG W=90n L=50n .ENDS cell_6t diff --git a/technology/scn3me_subm/sp_lib/cell_6t.sp b/technology/scn3me_subm/sp_lib/cell_6t.sp index 0310b9fe..76c40f31 100644 --- a/technology/scn3me_subm/sp_lib/cell_6t.sp +++ b/technology/scn3me_subm/sp_lib/cell_6t.sp @@ -1,10 +1,10 @@ *********************** "cell_6t" ****************************** .SUBCKT cell_6t bl br wl vdd gnd -M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u -M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u -M_3 br wl net_2 gnd n W='1.2u' L=0.6u -M_4 bl wl net_1 gnd n W='1.2u' L=0.6u -M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u -M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u +M_1 Q Qb vdd vdd p W='0.9u' L=1.2u +M_2 Qb Q vdd vdd p W='0.9u' L=1.2u +M_3 br wl Qb gnd n W='1.2u' L=0.6u +M_4 bl wl Q gnd n W='1.2u' L=0.6u +M_5 Qb Q gnd gnd n W='2.4u' L=0.6u +M_6 Q Qb gnd gnd n W='2.4u' L=0.6u .ENDS $ cell_6t diff --git a/technology/scn3me_subm/sp_lib/write_driver.sp b/technology/scn3me_subm/sp_lib/write_driver.sp index a203d1ba..edddf18c 100644 --- a/technology/scn3me_subm/sp_lib/write_driver.sp +++ b/technology/scn3me_subm/sp_lib/write_driver.sp @@ -2,28 +2,28 @@ .SUBCKT write_driver din bl br en vdd gnd **** Inverter to conver Data_in to data_in_bar ****** -M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u -M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u +M_1 din_bar din gnd gnd n W='1.2*1u' L=0.6u +M_2 din_bar din vdd vdd p W='2.1*1u' L=0.6u **** 2input nand gate follwed by inverter to drive BL ****** -M_3 net_2 en net_7 gnd n W='2.1*1u' L=0.6u +M_3 din_bar_gated en net_7 gnd n W='2.1*1u' L=0.6u M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u -M_5 net_2 en vdd vdd p W='2.1*1u' L=0.6u -M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u +M_5 din_bar_gated en vdd vdd p W='2.1*1u' L=0.6u +M_6 din_bar_gated din vdd vdd p W='2.1*1u' L=0.6u -M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u -M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u +M_7 net_1 din_bar_gated vdd vdd p W='2.1*1u' L=0.6u +M_8 net_1 din_bar_gated gnd gnd n W='1.2*1u' L=0.6u **** 2input nand gate follwed by inverter to drive BR****** -M_9 net_4 en vdd vdd p W='2.1*1u' L=0.6u -M_10 net_4 en net_8 gnd n W='2.1*1u' L=0.6u -M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u -M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u +M_9 din_gated en vdd vdd p W='2.1*1u' L=0.6u +M_10 din_gated en net_8 gnd n W='2.1*1u' L=0.6u +M_11 net_8 din_bar gnd gnd n W='2.1*1u' L=0.6u +M_12 din_gated din_bar vdd vdd p W='2.1*1u' L=0.6u -M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u -M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u +M_13 net_6 din_gated vdd vdd p W='2.1*1u' L=0.6u +M_14 net_6 din_gated gnd gnd n W='1.2*1u' L=0.6u ************************************************