From 35e1a523cceee5d6bc50d70065e30b424a384869 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 17 Nov 2020 14:29:01 -0800 Subject: [PATCH] Changed named on delay chain sizing variable. Automatic sizing default is False. --- compiler/characterizer/model_check.py | 4 ++-- compiler/options.py | 2 +- compiler/tests/21_hspice_delay_test.py | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py index 794b3988..4ff67b39 100644 --- a/compiler/characterizer/model_check.py +++ b/compiler/characterizer/model_check.py @@ -412,7 +412,7 @@ class model_check(delay): data_dict[self.bl_meas_name] = bl_delays[read_port] data_dict[self.power_name] = powers[read_port] - if not OPTS.use_tech_delay_chain_size: #Model is not used in this case + if OPTS.auto_delay_chain_sizing: #Model is not used in this case wl_model_delays, sae_model_delays = self.get_model_delays(read_port) debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays)) debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays)) @@ -439,7 +439,7 @@ class model_check(delay): name_dict[self.power_name] = self.power_meas_names #name_dict[self.wl_slew_name] = self.wl_slew_meas_names - if not OPTS.use_tech_delay_chain_size: + if OPTS.auto_delay_chain_sizing: name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured. name_dict[self.sae_model_name] = name_dict["sae_measures"] diff --git a/compiler/options.py b/compiler/options.py index ae9bc89d..75cd7a0a 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -60,7 +60,7 @@ class options(optparse.Values): rbl_delay_percentage = 0.5 # Allow manual adjustment of the delay chain over automatic - use_tech_delay_chain_size = False + auto_delay_chain_sizing = False delay_chain_stages = 9 delay_chain_fanout_per_stage = 4 diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index f7af5152..552308ed 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -38,7 +38,6 @@ class timing_sram_test(openram_test): # num_words=256, # num_banks=1) # c.words_per_row=2 - # OPTS.use_tech_delay_chain_size = True c.recompute_sizes() debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") s = factory.create(module_type="sram", sram_config=c)