From 35c162acbdd6919e01b6aa3c53c47e3339b6c6e9 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 19 Nov 2020 08:45:09 -0800 Subject: [PATCH] Use internal pin names in path names for signal traces. --- compiler/base/hierarchy_layout.py | 2 +- compiler/bitcells/bitcell_2port.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 00bd53fb..a3255075 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -377,7 +377,7 @@ class layout(): """ Return a pin list of all pins """ - return self.pin_map.keys() + return self.pins def copy_layout_pin(self, instance, pin_name, new_name=""): """ diff --git a/compiler/bitcells/bitcell_2port.py b/compiler/bitcells/bitcell_2port.py index 6a9f0b6f..fa790ef6 100644 --- a/compiler/bitcells/bitcell_2port.py +++ b/compiler/bitcells/bitcell_2port.py @@ -91,7 +91,7 @@ class bitcell_2port(bitcell_base.bitcell_base): def build_graph(self, graph, inst_name, port_nets): """Adds edges to graph. Multiport bitcell timing graph is too complex to use the add_graph_edges function.""" - pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)} + pin_dict = {pin: port for pin, port in zip(self.get_original_pin_names(), port_nets)} # Edges hardcoded here. Essentially wl->bl/br for both ports. # Port 0 edges graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)