From 3539887ee484479a0ef54abae202400d6fde560a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 13 Sep 2018 11:40:24 -0700 Subject: [PATCH] Updating ms_flop removal. Updated characterizer for dff. Added new setup/hold results for dff instead of ms_flop. Removed ms_flop references in sram-base. Fixed syntax errors in SCN3ME tech file. --- compiler/characterizer/setup_hold.py | 2 +- compiler/modules/bank.py | 2 +- compiler/modules/multibank.py | 2 +- compiler/options.py | 3 +-- compiler/sram_base.py | 4 ---- compiler/tests/04_precharge_test.py | 0 .../tests/04_single_level_column_mux_test.py | 0 .../07_single_level_column_mux_array_test.py | 0 compiler/tests/08_precharge_array_test.py | 0 compiler/tests/08_wordline_driver_test.py | 0 compiler/tests/09_sense_amp_array_test.py | 0 compiler/tests/10_write_driver_array_test.py | 0 compiler/tests/19_psingle_bank_test.py | 0 compiler/tests/20_psram_1bank_test.py | 0 compiler/tests/21_hspice_setuphold_test.py | 16 ++++++++-------- compiler/tests/21_ngspice_setuphold_test.py | 16 ++++++++-------- technology/scn4me_subm/tech/tech.py | 6 +++--- 17 files changed, 23 insertions(+), 28 deletions(-) mode change 100644 => 100755 compiler/tests/04_precharge_test.py mode change 100644 => 100755 compiler/tests/04_single_level_column_mux_test.py mode change 100644 => 100755 compiler/tests/07_single_level_column_mux_array_test.py mode change 100644 => 100755 compiler/tests/08_precharge_array_test.py mode change 100644 => 100755 compiler/tests/08_wordline_driver_test.py mode change 100644 => 100755 compiler/tests/09_sense_amp_array_test.py mode change 100644 => 100755 compiler/tests/10_write_driver_array_test.py mode change 100644 => 100755 compiler/tests/19_psingle_bank_test.py mode change 100644 => 100755 compiler/tests/20_psram_1bank_test.py diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index eaef6bac..8a515776 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -15,7 +15,7 @@ class setup_hold(): def __init__(self, corner): # This must match the spice model order - self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"] + self.pins = ["data", "dout", "clk", "vdd", "gnd"] self.model_name = "dff" self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c930d62a..d6c884a4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -206,7 +206,7 @@ class bank(design.design): def add_modules(self): """ Create all the modules using the class loader """ - mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "dff", "bank_select"] diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 3a63c890..e23fa6aa 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -23,7 +23,7 @@ class multibank(design.design): def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""): - mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "tri_gate_array", "dff", "bank_select"] diff --git a/compiler/options.py b/compiler/options.py index 4d522465..58d97ea0 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -71,8 +71,7 @@ class options(optparse.Values): # These are the default modules that can be over-riden decoder = "hierarchical_decoder" - ms_flop = "ms_flop" - ms_flop_array = "ms_flop_array" + dff_array = "dff_array" dff = "dff" control_logic = "control_logic" bitcell_array = "bitcell_array" diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 67789b78..9a511bd4 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -227,10 +227,6 @@ class sram_base(design): c = reload(__import__(OPTS.control_logic)) self.mod_control_logic = getattr(c, OPTS.control_logic) - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms_flop = self.mod_ms_flop() - from control_logic import control_logic # Create the control logic module diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/20_psram_1bank_test.py b/compiler/tests/20_psram_1bank_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index b123ed57..80568196 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.014648399999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0036620999999999997], - 'setup_times_HL': [0.0085449]} + golden_data = {'hold_times_HL': [-0.01586914], + 'hold_times_LH': [-0.01586914], + 'setup_times_HL': [0.02685547], + 'setup_times_LH': [0.03295898]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.08178709999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0646973], - 'setup_times_HL': [0.0390625]} + golden_data = {'hold_times_HL': [-0.15625], + 'hold_times_LH': [-0.1257324], + 'setup_times_HL': [0.2038574], + 'setup_times_LH': [0.2893066]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 849a23f0..df8c60de 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.01464844], - 'hold_times_LH': [0.0024414059999999997], - 'hold_times_HL': [-0.003662109], - 'setup_times_HL': [0.008544922]} + golden_data = {'hold_times_HL': [-0.01586914], + 'hold_times_LH': [-0.01586914], + 'setup_times_HL': [0.02685547], + 'setup_times_LH': [0.03295898]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.07568359], - 'hold_times_LH': [0.008544922], - 'hold_times_HL': [-0.05859374999999999], - 'setup_times_HL': [0.03295898]} + golden_data = {'hold_times_HL': [-0.15625], + 'hold_times_LH': [-0.1257324], + 'setup_times_HL': [0.2038574], + 'setup_times_LH': [0.2893066]} else: self.assertTrue(False) # other techs fail diff --git a/technology/scn4me_subm/tech/tech.py b/technology/scn4me_subm/tech/tech.py index 565d73bc..85285f84 100755 --- a/technology/scn4me_subm/tech/tech.py +++ b/technology/scn4me_subm/tech/tech.py @@ -184,7 +184,7 @@ drc["via2_to_via2"] = 3*_lambda_ # 15.1 Minimum width drc["minwidth_metal3"] = 3*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 3*_lamda_ +drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 drc["metal3_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures @@ -206,9 +206,9 @@ drc["via3_to_via3"] = 3*_lambda_ # 22.1 Minimum width drc["minwidth_metal3"] = 6*_lambda_ # 22.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 6*_lamda_ +drc["metal3_to_metal3"] = 6*_lambda_ # 22.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 2_lambda_ +drc["metal3_extend_via2"] = 2*_lambda_ # Reserved for asymmetric enclosures drc["metal3_enclosure_via2"] = 2*_lambda_ # Not a rule