diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index c930d62a..c6dde101 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -94,8 +94,7 @@ class bank(design.design):
         if self.num_banks > 1:
             for port in range(self.total_ports):
                 self.add_pin("bank_sel{}".format(port),"INPUT")
-        for port in range(self.total_read):
-            self.add_pin("s_en{0}".format(self.read_index[port]), "INPUT")
+        self.add_pin("s_en", "INPUT")
         for port in range(self.total_write):
             self.add_pin("w_en{0}".format(port), "INPUT")
         for pin in ["clk_buf_bar","clk_buf"]:
@@ -181,7 +180,7 @@ class bank(design.design):
         # Number of control lines in the bus
         self.num_control_lines = 4
         # The order of the control signals on the control bus:
-        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
+        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en"]
 
         # These will be outputs of the gaters if this is multibank, if not, normal signals.
         if self.num_banks > 1:
@@ -373,7 +372,7 @@ class bank(design.design):
                     temp.append(self.read_bl_list[port]+"_out[{0}]".format(bit))
                     temp.append(self.read_br_list[port]+"_out[{0}]".format(bit))
                     
-            temp.extend([self.prefix+"s_en{0}".format(port), "vdd", "gnd"])
+            temp.extend([self.prefix+"s_en", "vdd", "gnd"])
             self.connect_inst(temp)
 
     def place_sense_amp_array(self):
@@ -898,7 +897,7 @@ class bank(design.design):
         connection = []
         connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst[0].get_pin("en").lc()))
         connection.append((self.prefix+"w_en0", self.write_driver_array_inst[0].get_pin("en").lc()))
-        connection.append((self.prefix+"s_en0", self.sense_amp_array_inst[0].get_pin("en").lc()))
+        connection.append((self.prefix+"s_en", self.sense_amp_array_inst[0].get_pin("en").lc()))
   
         for (control_signal, pin_pos) in connection:
             control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y)
diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py
index 337deb48..037d1ca9 100644
--- a/compiler/modules/bank_select.py
+++ b/compiler/modules/bank_select.py
@@ -41,7 +41,7 @@ class bank_select(design.design):
         self.num_control_lines = 4
         # The order of the control signals on the control bus:
         # FIXME: Update for multiport (these names are not right)
-        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
+        self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en"]
         # These will be outputs of the gaters if this is multibank
         self.control_signals = ["gated_"+str for str in self.input_control_signals]
 
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 5d38f5a6..a54cc6e3 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -113,7 +113,7 @@ class control_logic(design.design):
         self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch 
         
         # Outputs to the bank
-        self.output_list = ["s_en0"]
+        self.output_list = ["s_en"]
         for port in range(self.total_write):
             self.output_list.append("w_en{}".format(port))
         self.output_list.append("clk_buf_bar")
@@ -253,7 +253,7 @@ class control_logic(design.design):
         # input: input: pre_s_en_bar, output: s_en
         self.s_en_inst=self.add_inst(name="inv_s_en",
                                      mod=self.inv8)
-        self.connect_inst(["pre_s_en_bar", "s_en0",  "vdd", "gnd"])
+        self.connect_inst(["pre_s_en_bar", "s_en",  "vdd", "gnd"])
         
     def place_sen_row(self,row):
         """ 
@@ -469,7 +469,7 @@ class control_logic(design.design):
 
         self.add_path("metal1",[self.pre_s_en_bar_inst.get_pin("Z").center(), self.s_en_inst.get_pin("A").center()])
 
-        self.connect_output(self.s_en_inst, "Z", "s_en0")
+        self.connect_output(self.s_en_inst, "Z", "s_en")
         
     def route_clk(self):
         """ Route the clk and clk_buf_bar signal internally """
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index c4c911de..21f00386 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -121,7 +121,7 @@ class sram_base(design):
         """ Add the horizontal and vertical busses """
         # Vertical bus
         # The order of the control signals on the control bus:
-        self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en0", "s_en0"]
+        self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en0", "s_en"]
         self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
                                                                    pitch=self.m2_pitch,
                                                                    offset=self.vertical_bus_offset,
@@ -286,8 +286,7 @@ class sram_base(design):
         if(self.num_banks > 1):
             for port in range(self.total_ports):
                 temp.append("bank_sel{0}[{1}]".format(port,bank_num))
-        for port in range(self.total_read):
-            temp.append("s_en{0}".format(self.read_index[port]))
+        temp.append("s_en")
         for port in range(self.total_write):
             temp.append("w_en{0}".format(port))
         temp.extend(["clk_buf_bar","clk_buf" , "vdd", "gnd"])
@@ -383,7 +382,7 @@ class sram_base(design):
         temp = ["csb"]
         for port in range(self.total_write):
             temp.append("web{}".format(port))
-        temp.extend(["clk", "s_en0"])
+        temp.extend(["clk", "s_en"])
         for port in range(self.total_write):
             temp.append("w_en{}".format(port))
         temp.extend(["clk_buf_bar", "clk_buf", "vdd", "gnd"])