From 3244e01ca1d516ede1c944040a4c1c9c87682ac8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 8 Oct 2018 09:56:39 -0700 Subject: [PATCH] Add copy power pin function --- compiler/base/hierarchy_layout.py | 16 +++++++++++++ compiler/modules/bank.py | 40 ++++++------------------------- compiler/pgates/pinvbuf.py | 27 ++++++++++++++------- compiler/sram_base.py | 15 +++++------- 4 files changed, 47 insertions(+), 51 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 0fc89e5d..60f4101a 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -885,6 +885,22 @@ class layout(lef.lef): width=xmax-xmin, height=ymax-ymin) + + def copy_power_pins(self, inst, name): + """ + This will copy a power pin if it is on M3. If it is on M1, it will add a power via too. + """ + pins=inst.get_pins(name) + for pin in pins: + if pin.layer=="metal3": + self.add_layout_pin(name, pin.layer, pin.ll(), pin.width(), pin.height()) + elif pin.layer=="metal1": + self.add_power_pin(name, pin.center()) + else: + debug.warning("{0} pins of {1} should be on metal3 or metal1 for supply router.".format(name,inst.name)) + + + def add_power_pin(self, name, loc, rotate=90): """ Add a single power pin from M3 down to M1 at the given center location diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d6c884a4..a807a2bf 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -515,10 +515,13 @@ class bank(design.design): # FIXME: place for multiport for port in range(self.total_ports): + col_decoder_inst = self.col_decoder_inst[port] + # Place the col decoder right aligned with row decoder x_off = -(self.central_bus_width + self.wordline_driver.width + self.col_decoder.width) y_off = -(self.col_decoder.height + 2*drc["well_to_well"]) - self.col_decoder_inst[port].place(vector(x_off,y_off)) + col_decoder_inst.place(vector(x_off,y_off)) + def create_bank_select(self): @@ -559,38 +562,9 @@ class bank(design.design): def route_vdd_gnd(self): """ Propagate all vdd/gnd pins up to this level for all modules """ - - # These are the instances that every bank has - top_instances = [self.bitcell_array_inst] - for port in range(self.total_read): - #top_instances.append(self.precharge_array_inst[port]) - top_instances.append(self.sense_amp_array_inst[port]) - for port in range(self.total_write): - top_instances.append(self.write_driver_array_inst[port]) - for port in range(self.total_ports): - top_instances.extend([self.row_decoder_inst[port], - self.wordline_driver_inst[port]]) - # Add these if we use the part... - if self.col_addr_size > 0: - top_instances.append(self.col_decoder_inst[port]) - #top_instances.append(self.col_mux_array_inst[port]) - - if self.num_banks > 1: - top_instances.append(self.bank_select_inst[port]) - - if self.col_addr_size > 0: - for port in range(self.total_ports): - self.copy_layout_pin(self.col_mux_array_inst[port], "gnd") - for port in range(self.total_read): - self.copy_layout_pin(self.precharge_array_inst[port], "vdd") - - for inst in top_instances: - # Column mux has no vdd - #if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst[0]): - self.copy_layout_pin(inst, "vdd") - # Precharge has no gnd - #if inst != self.precharge_array_inst[port]: - self.copy_layout_pin(inst, "gnd") + for inst in self.insts: + self.copy_power_pins(inst,"vdd") + self.copy_power_pins(inst,"gnd") def route_bank_select(self): """ Route the bank select logic. """ diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 425e468f..76b3c929 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -97,13 +97,13 @@ class pinvbuf(design.design): # Add INV1 to the left (capacitance shield) self.inv1_inst.place(vector(0,0)) - # Add INV2 to the right of INVX1 + # Add INV2 to the right of INV1 self.inv2_inst.place(vector(self.inv1_inst.rx(),0)) - # Add INV3 to the right of INVX2 + # Add INV3 to the right of INV2 self.inv3_inst.place(vector(self.inv2_inst.rx(),0)) - # Add INV4 flipped to the bottom aligned with INVX2 + # Add INV4 flipped to the bottom aligned with INV2 self.inv4_inst.place(offset=vector(self.inv2_inst.rx(),2*self.inv2.height), mirror = "MX") @@ -135,18 +135,27 @@ class pinvbuf(design.design): # Continous vdd rail along with label. vdd_pin=self.inv1_inst.get_pin("vdd") - self.add_power_pin(name="vdd", - loc=vdd_pin.lc()) + self.add_layout_pin(text="vdd", + layer="metal1", + offset=vdd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) # Continous vdd rail along with label. gnd_pin=self.inv4_inst.get_pin("gnd") - self.add_power_pin(name="gnd", - loc=gnd_pin.lc()) + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=gnd_pin.height()) # Continous gnd rail along with label. gnd_pin=self.inv1_inst.get_pin("gnd") - self.add_power_pin(name="gnd", - loc=gnd_pin.lc()) + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) z_pin = self.inv4_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 4ffd283c..9cad7fb6 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -113,10 +113,10 @@ class sram_base(design): def supply_route(self): """ Route the supply grid and connect the pins to them. """ - + for inst in self.insts: - self.copy_layout_pin(inst, "vdd") - self.copy_layout_pin(inst, "gnd") + self.copy_power_pins(inst,"vdd") + self.copy_power_pins(inst,"gnd") from supply_router import supply_router as router layer_stack =("metal3","via3","metal4") @@ -223,6 +223,7 @@ class sram_base(design): self.tri_gate_array_inst, self.row_decoder_inst, self.wordline_driver_inst] + # Add these if we use the part... if self.col_addr_size > 0: top_instances.append(self.col_decoder_inst) @@ -233,12 +234,8 @@ class sram_base(design): for inst in top_instances: - # Column mux has no vdd - if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst): - self.copy_layout_pin(inst, "vdd") - # Precharge has no gnd - if inst != self.precharge_array_inst: - self.copy_layout_pin(inst, "gnd") + self.copy_layout_pin(inst, "vdd") + self.copy_layout_pin(inst, "gnd") def add_multi_bank_modules(self):