From 3202e1eb099930345c81e7e70cdd60d371769062 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Thu, 25 Oct 2018 00:58:01 -0700 Subject: [PATCH] Altering comment code in simulation.py to match the needs of delay.py --- compiler/characterizer/functional.py | 22 ++++++++++++++-------- compiler/characterizer/simulation.py | 18 +++++------------- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index ab232843..d6579ab5 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -56,12 +56,14 @@ class functional(simulation): check = 0 # First cycle idle - self.add_noop_all_ports("0"*self.addr_size, "0"*self.word_size) + comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current) + self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size) # Write at least once addr = self.gen_addr() word = self.gen_data() - self.add_write(addr, word, 0) + comment = self.gen_cycle_comment("write", word, addr, 0, self.t_current) + self.add_write(comment, addr, word, 0) self.stored_words[addr] = word # Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously. @@ -70,7 +72,8 @@ class functional(simulation): if self.port_id[port] == "w": self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port) else: - self.add_read_one_port(addr, rw_read_din_data, word, port) + comment = self.gen_cycle_comment("read", word, addr, port, self.t_current) + self.add_read_one_port(comment, addr, rw_read_din_data, port) self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check]) check += 1 self.cycle_times.append(self.t_current) @@ -98,7 +101,8 @@ class functional(simulation): if addr in w_addrs: self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port) else: - self.add_write_one_port(addr, word, port) + comment = self.gen_cycle_comment("write", word, addr, port, self.t_current) + self.add_write_one_port(comment, addr, word, port) self.stored_words[addr] = word w_addrs.append(addr) else: @@ -107,7 +111,8 @@ class functional(simulation): if addr in w_addrs: self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port) else: - self.add_read_one_port(addr, rw_read_din_data, word, port) + comment = self.gen_cycle_comment("read", word, addr, port, self.t_current) + self.add_read_one_port(comment, addr, rw_read_din_data, port) self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check]) check += 1 @@ -115,7 +120,8 @@ class functional(simulation): self.t_current += self.period # Last cycle idle needed to correctly measure the value on the second to last clock edge - self.add_noop_all_ports("0"*self.addr_size, "0"*self.word_size) + comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current) + self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size) def read_stim_results(self): # Extrat DOUT values from spice timing.lis @@ -221,7 +227,7 @@ class functional(simulation): # Write debug comments to stim file self.sf.write("\n\n * Sequence of operations\n") - for comment in self.cycle_comments: + for comment in self.fn_cycle_comments: self.sf.write("*{}\n".format(comment)) # Generate data input bits @@ -266,7 +272,7 @@ class functional(simulation): t_intital=t_intital, t_final=t_final) - self.stim.write_control(self.cycle_times[-1] + self.period, runlvl=1) + self.stim.write_control(self.cycle_times[-1] + self.period) self.sf.close() diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 43ce75a5..3d156d2d 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -107,13 +107,11 @@ class simulation(): debug.error("Non-binary address string",1) bit -= 1 - def add_write(self, address, data, port): + def add_write(self, comment, address, data, port): """ Add the control values for a write cycle. """ debug.check(port in self.write_index, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_index)) - comment = self.gen_cycle_comment("write", data, address, port, self.t_current) debug.info(2, comment) self.fn_cycle_comments.append(comment) - self.append_cycle_comment(port, comment) self.cycle_times.append(self.t_current) @@ -130,13 +128,11 @@ class simulation(): if unselected_port != port: self.add_noop_one_port(address, noop_data, unselected_port) - def add_read(self, address, din_data, dout_data, port): + def add_read(self, comment, address, din_data, port): """ Add the control values for a read cycle. """ debug.check(port in self.read_index, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_index)) - comment = self.gen_cycle_comment("read", dout_data, address, port, self.t_current) debug.info(2, comment) self.fn_cycle_comments.append(comment) - self.append_cycle_comment(port, comment) self.cycle_times.append(self.t_current) @@ -155,12 +151,10 @@ class simulation(): if unselected_port != port: self.add_noop_one_port(address, noop_data, unselected_port) - def add_noop_all_ports(self, address, data): + def add_noop_all_ports(self, comment, address, data): """ Add the control values for a noop to all ports. """ - comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current) debug.info(2, comment) self.fn_cycle_comments.append(comment) - self.append_cycle_comment("All", comment) self.cycle_times.append(self.t_current) @@ -169,10 +163,9 @@ class simulation(): for port in range(self.total_ports): self.add_noop_one_port(address, data, port) - def add_write_one_port(self, address, data, port): + def add_write_one_port(self, comment, address, data, port): """ Add the control values for a write cycle. Does not increment the period. """ debug.check(port in self.write_index, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_index)) - comment = self.gen_cycle_comment("write", data, address, port, self.t_current) debug.info(2, comment) self.fn_cycle_comments.append(comment) @@ -180,10 +173,9 @@ class simulation(): self.add_data(data,port) self.add_address(address,port) - def add_read_one_port(self, address, din_data, dout_data, port): + def add_read_one_port(self, comment, address, din_data, port): """ Add the control values for a read cycle. Does not increment the period. """ debug.check(port in self.read_index, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_index)) - comment = self.gen_cycle_comment("read", dout_data, address, port, self.t_current) debug.info(2, comment) self.fn_cycle_comments.append(comment)