From 31d3e6cb26022e4cab05413daae63a55af2aa55c Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 6 Apr 2021 12:53:10 -0700 Subject: [PATCH] Change LWL layers --- compiler/modules/local_bitcell_array.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 67eac001..f0427c51 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -239,7 +239,12 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): out_loc = out_pin.lc() mid_loc = vector(self.wl_insts[port].lx() - 1.5 * self.m3_pitch, out_loc.y) in_loc = in_pin.rc() - self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc]) + + self.add_path(out_pin.layer, [out_loc, mid_loc]) + self.add_via_stack_center(from_layer=out_pin.layer, + to_layer=in_pin.layer, + offset=mid_loc) + self.add_path(in_pin.layer, [mid_loc, in_loc]) def get_main_array_top(self): return self.bitcell_array_inst.by() + self.bitcell_array.get_main_array_top()