diff --git a/compiler/base/verilog.v b/compiler/base/verilog.v
new file mode 100644
index 00000000..f782c9d7
--- /dev/null
+++ b/compiler/base/verilog.v
@@ -0,0 +1,78 @@
+// OpenRAM SRAM model
+// Words: #$WORDS$#
+// Word size: #$WORD_SIZE$#
+#<WRITE_SIZE_CMT
+// Write size: #$WRITE_SIZE$#
+#>WRITE_SIZE_CMT
+
+module #$MODULE_NAME$# (
+`ifdef USE_POWER_PINS
+    #$VDD$#,
+    #$GND$#,
+`endif
+#<RW_PORT
+// Port 0: RW
+    clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr0,din0,dout0
+#>RW_PORT
+  );
+
+  parameter DATA_WIDTH = 2 ;
+  parameter ADDR_WIDTH = 4 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vdd;
+    inout gnd;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    #(T_HOLD) dout0 = 2'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE )
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        mem[addr0_reg][1:0] = din0_reg[1:0];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+e