diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 3b2eb2d3..02b100ad 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -136,8 +136,7 @@ class geometry: def cy(self): """ Return the center y """ return 0.5 * (self.boundary[0].y + self.boundary[1].y) - - + class instance(geometry): """ An instance of an instance/module with a specified location and @@ -306,29 +305,47 @@ class instance(geometry): return (uVector, vVector, origin) def reverse_transformation_bitcell(self, cell_name): - path = [] - cell_paths = [] - origin_offsets = [] - Q_offsets = [] - Q_bar_offsets = [] - bl_offsets = [] - br_offsets = [] + path = [] # path currently follwed in bitcell search + cell_paths = [] # saved paths to bitcells + origin_offsets = [] # cell to bank offset + Q_offsets = [] # Q to cell offet + Q_bar_offsets = [] # Q_bar to cell offset + bl_offsets = [] # bl to cell offset + br_offsets = [] # br to cell offset + bl_meta = [] # bl offset metadata (row,col,name) + br_meta = [] #br offset metadata (row,col,name) def walk_subtree(node): path.append(node) if node.mod.name == cell_name: cell_paths.append(copy.copy(path)) + + inst_name = path[-1].name + # get the row and col names from the path + row = int(path[-1].name.split('_')[-2][1:]) + col = int(path[-1].name.split('_')[-1][1:]) + + cell_bl_meta = [] + cell_br_meta = [] + normalized_storage_nets = node.mod.get_normalized_storage_nets_offset() - (normalized_bl_offsets, normalized_br_offsets) = node.mod.get_normalized_bitline_offset() + (normalized_bl_offsets, normalized_br_offsets, bl_names, br_names) = node.mod.get_normalized_bitline_offset() + + for offset in range(len(normalized_bl_offsets)): + for port in range(len(bl_names)): + cell_bl_meta.append([bl_names[offset], row, col, port]) + + for offset in range(len(normalized_br_offsets)): + for port in range(len(br_names)): + cell_br_meta.append([br_names[offset], row, col, port]) Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] Q_bar_x = normalized_storage_nets[1][0] Q_bar_y = normalized_storage_nets[1][1] - if node.mirror == 'MX': Q_y = -1 * Q_y @@ -350,6 +367,9 @@ class instance(geometry): bl_offsets.append(normalized_bl_offsets) br_offsets.append(normalized_br_offsets) + bl_meta.append(cell_bl_meta) + br_meta.append(cell_br_meta) + elif node.mod.insts is not []: for instance in node.mod.insts: walk_subtree(instance) @@ -361,7 +381,7 @@ class instance(geometry): origin = vector_spaces[2] origin_offsets.append([origin[0], origin[1]]) - return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets) + return(origin_offsets, Q_offsets, Q_bar_offsets, bl_offsets, br_offsets, bl_meta, br_meta) def __str__(self): """ override print function output """ diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 069f8f6c..58f7bdcb 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -116,6 +116,7 @@ class bitcell_base(design.design): if bl_names[i] == text.textString.rstrip('\x00'): self.bl_offsets.append(text.coordinates[0]) found_bl.append(bl_names[i]) + continue for i in range(len(br_names)): @@ -132,7 +133,7 @@ class bitcell_base(design.design): for i in range(len(self.br_offsets)): self.br_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.br_offsets[i]]) - return(self.bl_offsets, self.br_offsets) + return(self.bl_offsets, self.br_offsets, found_bl, found_br) def get_normalized_storage_nets_offset(self): """ diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 4b6584d4..fde94de0 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -1,9 +1,9 @@ word_size = 2 num_words = 16 -num_rw_ports = 1 +num_rw_ports = 0 num_r_ports = 1 -num_w_ports = 0 +num_w_ports = 1 tech_name = "scn4m_subm" process_corners = ["TT"] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3479957b..8d4bc330 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -95,13 +95,15 @@ class sram_base(design, verilog, lef): # add pex labels for bitcells for bank_num in range(len(self.bank_insts)): bank = self.bank_insts[bank_num] - pex_offsets = bank.reverse_transformation_bitcell(bank.mod.bitcell.name) + pex_data = bank.reverse_transformation_bitcell(bank.mod.bitcell.name) - bank_offset = pex_offsets[0] # offset bank relative to sram - Q_offset = pex_offsets[1] # offset of storage relative to bank - Q_bar_offset = pex_offsets[2] # offset of storage relative to bank - bl_offsets = pex_offsets[3] - br_offsets = pex_offsets[4] + bank_offset = pex_data[0] # offset bank relative to sram + Q_offset = pex_data[1] # offset of storage relative to bank + Q_bar_offset = pex_data[2] # offset of storage relative to bank + bl_offsets = pex_data[3] + br_offsets = pex_data[4] + bl_meta = pex_data[5] + br_meta = pex_data[6] bl = [] br = [] @@ -116,20 +118,26 @@ class sram_base(design, verilog, lef): self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q) self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar) + for cell in range(len(bl_offsets)): + col = bl_meta[cell][0][2] for bitline in range(len(bl_offsets[cell])): bitline_location = [float(bank_offset[cell][0]) + bl_offsets[cell][bitline][0], float(bank_offset[cell][1]) + bl_offsets[cell][bitline][1]] - bl.append(bitline_location) + bl.append([bitline_location, bl_meta[cell][bitline][3], col]) - for bitline in range(len(br_offsets[0])): + for cell in range(len(br_offsets)): + col = br_meta[cell][0][2] + for bitline in range(len(br_offsets[cell])): bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]] - br.append(bitline_location) - - for col in range(len(bl)): - self.add_layout_pin_rect_center("bl{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, bl[col]) + br.append([bitline_location, br_meta[cell][bitline][3], col]) - for col in range(len(br)): - self.add_layout_pin_rect_center("br{0}_{1}".format(bank_num, int(col / OPTS.num_words)), bitline_layer_name, br[col]) - + + + + for i in range(len(bl)): + self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0]) + + for i in range(len(br)): + self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) diff --git a/technology/scn4m_subm/gds_lib/cell_1w_1r.gds b/technology/scn4m_subm/gds_lib/cell_1w_1r.gds index 782c43dc..06f79ba5 100644 Binary files a/technology/scn4m_subm/gds_lib/cell_1w_1r.gds and b/technology/scn4m_subm/gds_lib/cell_1w_1r.gds differ