From 2ed107f9ffe52f78b654bf1360ed9ade4c0f90c7 Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Thu, 4 Aug 2022 16:36:26 -0700 Subject: [PATCH] Fix the total addr_size --- compiler/modules/sram_config.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/sram_config.py b/compiler/modules/sram_config.py index ac62886d..9cdfd7c4 100644 --- a/compiler/modules/sram_config.py +++ b/compiler/modules/sram_config.py @@ -121,12 +121,14 @@ class sram_config: self.row_addr_size = ceil(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size - #self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) - self.addr_size = self.bank_addr_size + self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) + #self.addr_size = self.bank_addr_size debug.info(1, "Row addr size: {}".format(self.row_addr_size) + " Col addr size: {}".format(self.col_addr_size) + " Bank addr size: {}".format(self.bank_addr_size)) + + num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports if num_ports == 1: if ((self.num_cols + num_ports + self.num_spare_cols) % self.array_col_multiple != 0):