From 2ce7323838df9f9b0f8e8c414acf420a1746d49a Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 6 Aug 2019 17:09:25 -0700 Subject: [PATCH] Removed all unused analytical delay functions. --- compiler/modules/control_logic.py | 3 ++- compiler/modules/dff.py | 5 ---- compiler/modules/dff_array.py | 5 ---- compiler/modules/dff_buf.py | 11 +-------- compiler/modules/dff_buf_array.py | 5 ---- compiler/modules/dff_inv.py | 10 +------- compiler/modules/dff_inv_array.py | 6 ----- compiler/modules/hierarchical_decoder.py | 22 ----------------- compiler/modules/hierarchical_predecode2x4.py | 19 +-------------- compiler/modules/hierarchical_predecode3x8.py | 19 +-------------- compiler/modules/multibank.py | 20 +--------------- compiler/modules/tri_gate.py | 6 ----- compiler/modules/tri_gate_array.py | 8 +------ compiler/modules/wordline_driver.py | 15 ------------ compiler/pgates/pand2.py | 8 ------- compiler/pgates/pbuf.py | 8 ------- compiler/pgates/pdriver.py | 24 ------------------- compiler/pgates/pinv.py | 9 ------- compiler/pgates/pinvbuf.py | 10 +------- compiler/pgates/pnand2.py | 11 --------- compiler/pgates/pnand3.py | 10 -------- compiler/pgates/pnor2.py | 10 -------- compiler/pgates/ptristate_inv.py | 7 ------ 23 files changed, 9 insertions(+), 242 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 1d2226b1..372820d9 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -921,7 +921,8 @@ class control_logic(design.design): last_stage_rise = False #First stage(s), clk -(pdriver)-> clk_buf. - clk_buf_cout = self.replica_bitline.get_en_cin() + #clk_buf_cout = self.replica_bitline.get_en_cin() + clk_buf_cout = 0 stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise) last_stage_rise = stage_effort_list[-1].is_rise diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index c8d7414a..083d92b7 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -48,11 +48,6 @@ class dff(design.design): transition_prob = spice["flop_transition_prob"] return transition_prob*(c_load + c_para) - def analytical_delay(self, corner, slew, load = 0.0): - # dont know how to calculate this now, use constant in tech file - result = self.return_delay(spice["dff_delay"], spice["dff_slew"]) - return result - def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" #This is a handmade cell so the value must be entered in the tech.py file or estimated. diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 32b36765..89b29476 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -160,11 +160,6 @@ class dff_array(design.design): self.add_via_center(layers=("metal2","via2","metal3"), offset=vector(clk_pin.cx(),clk_ypos)) - - - def analytical_delay(self, corner, slew, load=0.0): - return self.dff.analytical_delay(corner, slew=slew, load=load) - def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" dff_clk_cin = self.dff.get_clk_cin() diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9359329a..f6fc1cf2 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -177,16 +177,7 @@ class dff_buf(design.design): self.add_path("metal1", [self.mid_qb_pos, qb_pos]) self.add_via_center(layers=("metal1","via1","metal2"), offset=qb_pos) - - - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - dff_delay=self.dff.analytical_delay(corner, slew=slew, load=self.inv1.input_load()) - inv1_delay = self.inv1.analytical_delay(corner, slew=dff_delay.slew, load=self.inv2.input_load()) - inv2_delay = self.inv2.analytical_delay(corner, slew=inv1_delay.slew, load=load) - return dff_delay + inv1_delay + inv2_delay - + def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" #This is a handmade cell so the value must be entered in the tech.py file or estimated. diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index df36b2aa..2fafee76 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -193,11 +193,6 @@ class dff_buf_array(design.design): self.add_via_center(layers=("metal2","via2","metal3"), offset=vector(clk_pin.cx(),clk_ypos)) - - - def analytical_delay(self, corner, slew, load=0.0): - return self.dff.analytical_delay(slew=slew, load=load) - def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" dff_clk_cin = self.dff.get_clk_cin() diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 226db290..207a5ad0 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -150,15 +150,7 @@ class dff_inv(design.design): offset=dout_pin.center()) self.add_via_center(layers=("metal1","via1","metal2"), offset=dout_pin.center()) - - - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - dff_delay=self.dff.analytical_delay(corner, slew=slew, load=self.inv1.input_load()) - inv1_delay = self.inv1.analytical_delay(corner, slew=dff_delay.slew, load=load) - return dff_delay + inv1_delay - + def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff""" return self.dff.get_clk_cin() diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 051dd237..760a2337 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -190,12 +190,6 @@ class dff_inv_array(design.design): self.add_via_center(layers=("metal2","via2","metal3"), offset=vector(clk_pin.cx(),clk_ypos)) - - - - def analytical_delay(self, corner, slew, load=0.0): - return self.dff.analytical_delay(corner, slew=slew, load=load) - def get_clk_cin(self): """Return the total capacitance (in relative units) that the clock is loaded by in the dff array""" dff_clk_cin = self.dff.get_clk_cin() diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 75eb3345..0e70db55 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -596,28 +596,6 @@ class hierarchical_decoder(design.design): self.add_via_center(layers=("metal2", "via2", "metal3"), offset=rail_pos) - - def analytical_delay(self, corner, slew, load = 0.0): - # A -> out - if self.determine_predecodes(self.num_inputs)[1]==0: - pre = self.pre2_4 - nand = self.nand2 - else: - pre = self.pre3_8 - nand = self.nand3 - a_t_out_delay = pre.analytical_delay(corner, slew=slew,load = nand.input_load()) - - # out -> z - out_t_z_delay = nand.analytical_delay(corner, slew= a_t_out_delay.slew, - load = self.inv.input_load()) - result = a_t_out_delay + out_t_z_delay - - # Z -> decode_out - z_t_decodeout_delay = self.inv.analytical_delay(corner, slew = out_t_z_delay.slew , load = load) - result = result + z_t_decodeout_delay - return result - - def input_load(self): if self.determine_predecodes(self.num_inputs)[1]==0: pre = self.pre2_4 diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 56046c74..f05f54b0 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -56,21 +56,4 @@ class hierarchical_predecode2x4(hierarchical_predecode): ["A_0", "Abar_1"], ["Abar_0", "A_1"], ["A_0", "A_1"]] - return combination - - - def analytical_delay(self, corner, slew, load = 0.0 ): - # in -> inbar - a_t_b_delay = self.inv.analytical_delay(corner, slew=slew, load=self.nand.input_load()) - - # inbar -> z - b_t_z_delay = self.nand.analytical_delay(corner, slew=a_t_b_delay.slew, load=self.inv.input_load()) - - # Z -> out - a_t_out_delay = self.inv.analytical_delay(corner, slew=b_t_z_delay.slew, load=load) - - return a_t_b_delay + b_t_z_delay + a_t_out_delay - - - def input_load(self): - return self.nand.input_load() + return combination \ No newline at end of file diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index a7794395..20b629bb 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -65,21 +65,4 @@ class hierarchical_predecode3x8(hierarchical_predecode): ["A_0", "Abar_1", "A_2"], ["Abar_0", "A_1", "A_2"], ["A_0", "A_1", "A_2"]] - return combination - - - def analytical_delay(self, corner, slew, load = 0.0 ): - # A -> Abar - a_t_b_delay = self.inv.analytical_delay(corner, slew=slew, load=self.nand.input_load()) - - # Abar -> z - b_t_z_delay = self.nand.analytical_delay(corner, slew=a_t_b_delay.slew, load=self.inv.input_load()) - - # Z -> out - a_t_out_delay = self.inv.analytical_delay(corner, slew=b_t_z_delay.slew, load=load) - - return a_t_b_delay + b_t_z_delay + a_t_out_delay - - - def input_load(self): - return self.nand.input_load() + return combination \ No newline at end of file diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index fd061273..28f689f7 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -827,22 +827,4 @@ class multibank(design.design): rotate=90) self.add_via(layers=("metal2","via2","metal3"), offset=in_pin + self.m2m3_via_offset, - rotate=90) - - def analytical_delay(self, corner, slew, load): - """ return analytical delay of the bank""" - decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load()) - - word_driver_delay = self.wordline_driver.analytical_delay(corner, decoder_delay.slew, self.bitcell_array.input_load()) - - bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew) - - bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner, bitcell_array_delay.slew, - self.bitcell_array.output_load()) - # output load of bitcell_array is set to be only small part of bl for sense amp. - - data_t_DATA_delay = self.tri_gate_array.analytical_delay(corner, bl_t_data_out_delay.slew, load) - - result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay - return result - + rotate=90) \ No newline at end of file diff --git a/compiler/modules/tri_gate.py b/compiler/modules/tri_gate.py index 3907a03b..fe59e7b9 100644 --- a/compiler/modules/tri_gate.py +++ b/compiler/modules/tri_gate.py @@ -36,12 +36,6 @@ class tri_gate(design.design): self.pin_map = tri_gate.pin_map self.add_pin_types(self.type_list) - def analytical_delay(self, corner, slew, load=0.0): - from tech import spice - r = spice["min_tx_r"] - c_para = spice["min_tx_drain_c"] - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" #Power in this module currently not defined. Returns 0 nW (leakage and dynamic). diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index df39ad96..7d1c21d0 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -120,10 +120,4 @@ class tri_gate_array(design.design): layer="metal1", offset=enbar_pin.ll().scale(0, 1), width=width, - height=drc("minwidth_metal1")) - - - - def analytical_delay(self, corner, slew, load=0.0): - return self.tri.analytical_delay(corner, slew = slew, load = load) - + height=drc("minwidth_metal1")) \ No newline at end of file diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 39700799..b1292560 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -210,21 +210,6 @@ class wordline_driver(design.design): start=wl_offset, end=wl_offset-vector(self.m1_width,0)) - - def analytical_delay(self, corner, slew, load=0): - # decode -> net - decode_t_net = self.nand2.analytical_delay(corner, slew, self.inv.input_load()) - - # net -> wl - net_t_wl = self.inv.analytical_delay(corner, decode_t_net.slew, load) - - return decode_t_net + net_t_wl - - - def input_load(self): - """Gets the capacitance of the wordline driver in absolute units (fF)""" - return self.nand2.input_load() - def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True): """Follows the clk_buf to a wordline signal adding each stages stage effort to a list""" stage_effort_list = [] diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index d299cc56..48f111c7 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -110,14 +110,6 @@ class pand2(pgate.pgate): width=pin.width(), height=pin.height()) - - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - nand_delay = self.nand.analytical_delay(corner, slew=slew, load=self.inv.input_load()) - inv_delay = self.inv.analytical_delay(corner, slew=nand_delay.slew, load=load) - return nand_delay + inv_delay - def get_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the A or B -> Z path""" stage_effort_list = [] diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 125a1190..fcfc6586 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -113,14 +113,6 @@ class pbuf(pgate.pgate): width=a_pin.width(), height=a_pin.height()) - - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - inv1_delay = self.inv1.analytical_delay(corner, slew=slew, load=self.inv2.input_load()) - inv2_delay = self.inv2.analytical_delay(corner, slew=inv1_delay.slew, load=load) - return inv1_delay + inv2_delay - def get_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the A -> Z path""" stage_effort_list = [] diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index a3180006..36811a5e 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -173,30 +173,6 @@ class pdriver(pgate.pgate): offset=a_pin.center(), width = a_pin.width(), height = a_pin.height()) - - def input_load(self): - return self.inv_list[0].input_load() - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of INV1 -> ... -> INVn """ - - cout_list = [] - for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]): - cout_list.append(inv.input_load()) - cout_list.append(load) - - input_slew = slew - - delays = [] - for inv,cout in zip(self.inv_list,cout_list): - delays.append(inv.analytical_delay(corner, slew=input_slew, load=cout)) - input_slew = delays[-1].slew - - delay = delays[0] - for i in range(len(delays)-1): - delay += delays[i] - - return delay def get_sizes(self): """ Return the relative sizes of the buffers """ diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 773a0452..28eb03e8 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -255,15 +255,6 @@ class pinv(pgate.pgate): self.connect_pin_to_rail(self.pmos_inst,"S","vdd") - - def input_load(self): - return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] - - def analytical_delay(self, corner, slew, load=0.0): - r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) - c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 72ab6a8a..a8d2c8b8 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -178,15 +178,7 @@ class pinvbuf(pgate.pgate): offset=a_pin.center()) self.add_via_center(layers=("metal1","via1","metal2"), offset=a_pin.center()) - - - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - inv1_delay = self.inv1.analytical_delay(corner, slew=slew, load=self.inv2.input_load()) - inv2_delay = self.inv2.analytical_delay(corner, slew=inv1_delay.slew, load=load) - return inv1_delay + inv2_delay - + def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False): """Get the stage efforts of the clk -> clk_buf path""" stage_effort_list = [] diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 956f0a30..b0d30b7b 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -233,17 +233,6 @@ class pnand2(pgate.pgate): width=contact.m1m2.first_layer_height, height=contact.m1m2.first_layer_width) - - - - def input_load(self): - return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] - - def analytical_delay(self, corner, slew, load=0.0): - r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) - c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 30da9165..eee6ca9a 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -243,16 +243,6 @@ class pnand3(pgate.pgate): width=contact.m1m2.first_layer_width, height=contact.m1m2.first_layer_height) - - - def input_load(self): - return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] - - def analytical_delay(self, corner, slew, load=0.0): - r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) - c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index fa52c528..ee55dbcb 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -213,16 +213,6 @@ class pnor2(pgate.pgate): width=contact.m1m2.first_layer_height, height=contact.m1m2.first_layer_width) - - - def input_load(self): - return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] - - def analytical_delay(self, corner, slew, load=0.0): - r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) - c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" c_eff = self.calculate_effective_capacitance(load) diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 55a248a7..3176915a 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -210,13 +210,6 @@ class ptristate_inv(pgate.pgate): self.connect_pin_to_rail(self.nmos1_inst,"S","gnd") self.connect_pin_to_rail(self.pmos1_inst,"S","vdd") - - def analytical_delay(self, corner, slew, load=0.0): - from tech import spice - r = spice["min_tx_r"] - c_para = spice["min_tx_drain_c"] - return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew) - def analytical_power(self, corner, load): """Returns dynamic and leakage power. Results in nW""" #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).