diff --git a/compiler/sram/sram_multibank_template.v b/compiler/sram/sram_multibank_template.v
index f26643d8..86b1dc2e 100644
--- a/compiler/sram/sram_multibank_template.v
+++ b/compiler/sram/sram_multibank_template.v
@@ -9,7 +9,9 @@ module {{ module_name }}  (
     addr{{ port }},
     din{{ port }},
     csb{{ port }},
+    {% if write_size > 1 %}
     wmask{{ port }},
+    {% endif %}
     web{{ port }},
     dout{{ port }},
 {% endfor %}
@@ -24,7 +26,9 @@ module {{ module_name }}  (
     addr{{ port }},
     din{{ port }},
     csb{{ port }},
+    {% if write_size > 1 %}
     wmask{{ port }},
+    {% endif %}
     web{{ port }},
 {% endfor %}
   );
@@ -36,8 +40,8 @@ module {{ module_name }}  (
   parameter NUM_WMASK = {{ num_wmask }};
 
 `ifdef USE_POWER_PINS
-  inout vdd;
-  inout gnd;
+  inout {{ vdd }};
+  inout {{ gnd }};
 `endif
 {% for port in rw_ports %}
   input clk{{ port }};
@@ -45,7 +49,9 @@ module {{ module_name }}  (
   input [DATA_WIDTH - 1: 0] din{{ port }};
   input csb{{ port }};
   input web{{ port }};
+  {% if write_size > 1 %}
   input [NUM_WMASK - 1 : 0] wmask{{ port }};
+  {% endif %}
   output reg [DATA_WIDTH - 1 : 0] dout{{ port }};
 {% endfor %}
 {% for port in r_ports %}
@@ -60,7 +66,9 @@ module {{ module_name }}  (
   input [DATA_WIDTH - 1: 0] din{{ port }};
   input csb{{ port }};
   input web{{ port }};
+  {% if write_size > 1 %}
   input [NUM_WMASK - 1 : 0] wmask{{ port }};
+  {% endif %}
 {% endfor %}
 
 {% for port in ports %}
@@ -79,8 +87,8 @@ module {{ module_name }}  (
 {% for bank in banks %}
   {{ bank_module_name }} bank{{ bank }} (
 `ifdef USE_POWER_PINS
-    .vdd(vdd),
-    .gnd(gnd),
+    .{{ vdd }}({{ vdd }}),
+    .{{ gnd }}({{ gnd }}),
 `endif
 {% for port in rw_ports %}
     .clk{{ port }}(clk{{ port }}),
@@ -88,7 +96,9 @@ module {{ module_name }}  (
     .din{{ port }}(din{{ port }}),
     .csb{{ port }}(csb{{ port }}_bank{{ bank }}),
     .web{{ port }}(web{{ port }}_bank{{ bank }}),
+    {% if write_size > 1 %}
     .wmask{{ port }}(wmask{{ port }}),
+    {% endif %}
     .dout{{ port }}(dout{{ port }}_bank{{ bank }}),
 {% endfor %}
 {% for port in r_ports %}
@@ -102,8 +112,10 @@ module {{ module_name }}  (
     .addr{{ port }}(addr{{ port }}[ADDR_WIDTH - BANK_SEL - 1 : 0]),
     .din{{ port }}(din{{ port }}),
     .csb{{ port }}(csb{{ port }}_bank{{ bank }}),
-    .web{{ port }}(web{{ port }}_bank{{ bank }}),
+    {% if write_size > 1 %}
     .wmask{{ port }}(wmask{{ port }}),
+    {% endif %}
+    .web{{ port }}(web{{ port }}_bank{{ bank }}),
 {% endfor %}
   );
 {% endfor %}
diff --git a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log b/compiler/tests/sram_1b_16_1rw_scn4m_subm.log
deleted file mode 100644
index 1d80b5f9..00000000
--- a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log
+++ /dev/null
@@ -1,2 +0,0 @@
-ERROR: file magic.py: line 358: sram	LVS mismatch (results in /tmp/openram_bugra_12868_temp/sram.lvs.report)
-
diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log
deleted file mode 100644
index f6367750..00000000
--- a/compiler/tests/sram_1b_16_1rw_sky130.log
+++ /dev/null
@@ -1,3 +0,0 @@
-ERROR: file design.py: line 47: Custom cell pin names do not match spice file:
-['D', 'Q', 'CLK', 'VDD', 'GND'] vs []
-
diff --git a/compiler/verilog_template/template.py b/compiler/verilog_template/template.py
index 623ceb41..e9399d22 100644
--- a/compiler/verilog_template/template.py
+++ b/compiler/verilog_template/template.py
@@ -1,7 +1,18 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California
+# Santa Cruz
+# All rights reserved.
+#
 import re
 
 
 class baseSection:
+    """
+    This is the base section class for other section classes to inherit.
+    It is also used as the top most section.
+    """
+
     children = []
 
     def expand(self, dict, fd):
@@ -10,9 +21,11 @@ class baseSection:
 
 
 class loopSection(baseSection):
-
+    """
+    This section is for looping elements. It will repeat the children
+    sections based on the key list.
+    """
     def __init__(self, var, key):
-        self.children = []
         self.var = var
         self.key = key
 
@@ -25,14 +38,33 @@ class loopSection(baseSection):
             del dict[self.var]
 
 
+class conditionalSection(baseSection):
+    """
+    This class will conditionally print it's children based on the 'cond'
+    element.
+    """
+    def __init__(self, cond):
+        self.cond = cond
+
+    def expand(self, dict, fd):
+        run = eval(self.cond, dict)
+        if run:
+            for c in self.children:
+                c.expand(dict, fd)
+
+
 class textSection(baseSection):
+    """
+    This is plain text section. It can contain parameters that can be
+    replaced based on the dictionary.
+    """
 
     def __init__(self, text):
         self.text = text
 
     def expand(self, dict, fd):
-        var_re = re.compile('\{\{ (\S*) \}\}')
-        vars = var_re.finditer(self.text)
+        varRE = re.compile('\{\{ (\S*) \}\}')
+        vars = varRE.finditer(self.text)
         newText = self.text
         for var in vars:
             newText = newText.replace('{{ ' + var.group(1) + ' }}', str(dict[var.group(1)]))
@@ -40,6 +72,10 @@ class textSection(baseSection):
 
 
 class template:
+    """
+    The template class will read a template and generate an output file
+    based on the template and the given dictionary.
+    """
 
     def __init__(self, template, dict):
         self.template = template
@@ -53,17 +89,26 @@ class template:
         self.baseSectionSection = baseSection()
         sections = []
         context = [self.baseSectionSection]
-        for_re = re.compile('\{% for (\S*) in (\S*) %\}')
-        end_re = re.compile('\{% endfor %\}')
+        forRE = re.compile('\{% for (\S*) in (\S*) %\}')
+        endforRE = re.compile('\{% endfor %\}')
+        ifRE = re.compile('\{% if (.*) %\}')
+        endifRE = re.compile('\{% endif %\}')
         for line in lines:
-            m = for_re.match(line)
+            m = forRE.match(line)
             if m:
                 section = loopSection(m.group(1), m.group(2))
                 sections.append(section)
                 context[-1].children.append(section)
                 context.append(section)
                 continue
-            if end_re.match(line):
+            m = ifRE.match(line)
+            if m:
+                section = conditionalSection(m.group(1))
+                section.append(section)
+                context[-1].children.append(section)
+                context.append(section)
+                continue
+            if endforRE.match(line) or endifRE.match(line):
                 context.pop()
             else:
                 context[-1].children.append(textSection(line))
diff --git a/compiler/verilog_template/test.py b/compiler/verilog_template/test.py
deleted file mode 100644
index 228b5042..00000000
--- a/compiler/verilog_template/test.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from template import template
-
-dict = {
-        'module_name': 'sram_1kbyte_32b_2bank', 
-        'bank_module_name': 'sram_1kbyte_32b_2bank_1bank', 
-        'vdd': 'vdd', 
-        'gnd': 'gnd', 
-        'ports': [0, 1], 
-        'rw_ports': [0], 
-        'r_ports': [1], 
-        'w_ports': [],
-        'banks': [0, 1],
-        'data_width': 32, 
-        'addr_width': 8,
-        'bank_sel': 1,
-        'num_wmask': 4
-        }
-t = template('../sram/sram_multibank_template.v', dict)
-t.write(dict['module_name'] + '.v')
-