From 29f19ad70f58ffd1c118d548bda63d7660c75ec5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 20 Nov 2018 12:27:54 -0800 Subject: [PATCH] replaced absolute links with relative links --- compiler/datasheet/datasheet_gen.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index b48c2510..efb3780c 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -470,11 +470,11 @@ def parse_characterizer_csv(sram,f,pages): new_sheet.dlv.append(deliverables_item('.lef','LEF files','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'lef'))) - new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'sp'))) - new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'v'))) - new_sheet.dlv.append(deliverables_item('.html','This datasheet','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'html'))) - new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'lib')))) - new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{1}.{2}'.format(OUT_DIR,OPTS.output_name,'py'))) + new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','{0}.{1}'.format(OPTS.output_name,'sp'))) + new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','{0}.{1}'.format(OPTS.output_name,'v'))) + new_sheet.dlv.append(deliverables_item('.html','This datasheet','{0}.{1}'.format(OPTS.output_name,'html'))) + new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,'')))) + new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','{0}.{1}'.format(OPTS.output_name,'py')))