diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 8a7b4bfe..854eeb75 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -10,7 +10,7 @@ from globals import OPTS class delay(): """ - Functions to measure the delay of the SRAM at a given address and + Functions to measure the delay of an SRAM at a given address and data bit. """ @@ -60,59 +60,57 @@ class delay(): # add vdd/gnd statements - self.sf.write("* Global Power Supplies\n") + self.sf.write("\n* Global Power Supplies\n") stimuli.write_supply(self.sf) # instantiate the sram - self.sf.write("* Instantiation of the SRAM\n") + self.sf.write("\n* Instantiation of the SRAM\n") stimuli.inst_sram(stim_file=self.sf, abits=self.addr_size, dbits=self.word_size, sram_name=self.name) - self.sf.write("* SRAM output loads\n") + self.sf.write("\n* SRAM output loads\n") for i in range(self.word_size): self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,load)) # add access transistors for data-bus - self.sf.write("* Transmission Gates for data-bus and control signals\n") + self.sf.write("\n* Transmission Gates for data-bus and control signals\n") stimuli.inst_accesstx(stim_file=self.sf, dbits=self.word_size) # generate data and addr signals - self.sf.write("* Generation of data and address signals\n") + self.sf.write("\n* Generation of data and address signals\n") for i in range(self.word_size): if i == self.probe_data: - stimuli.gen_data(stim_file=self.sf, - clk_times=self.cycle_times, - sig_name="data[{0}]".format(i), - period=period, - slew=slew) + self.gen_data(clk_times=self.cycle_times, + sig_name="data[{0}]".format(i), + period=period, + slew=slew) else: stimuli.gen_constant(stim_file=self.sf, sig_name="d[{0}]".format(i), v_val=self.gnd) - stimuli.gen_addr(self.sf, - clk_times=self.cycle_times, + self.gen_addr(clk_times=self.cycle_times, addr=self.probe_address, period=period, slew=slew) # generate control signals - self.sf.write("* Generation of control signals\n") - stimuli.gen_csb(self.sf, self.cycle_times, period, slew) - stimuli.gen_web(self.sf, self.cycle_times, period, slew) - stimuli.gen_oeb(self.sf, self.cycle_times, period, slew) + self.sf.write("\n* Generation of control signals\n") + self.gen_csb(self.cycle_times, period, slew) + self.gen_web(self.cycle_times, period, slew) + self.gen_oeb(self.cycle_times, period, slew) - self.sf.write("* Generation of global clock signal\n") + self.sf.write("\n* Generation of global clock signal\n") stimuli.gen_pulse(stim_file=self.sf, sig_name="CLK", v1=self.gnd, v2=self.vdd, offset=period, period=period, - t_rise = slew, - t_fall = slew) + t_rise=slew, + t_fall=slew) self.write_measures(period) @@ -122,17 +120,23 @@ class delay(): self.sf.close() def write_measures(self,period): - # meas statement for delay and power measurements - self.sf.write("* Measure statements for delay and power\n") + """ + Write the measure statements to quantify the delay and power results. + """ + self.sf.write("\n* Measure statements for delay and power\n") + + # Output some comments to aid where cycles start and + # what is happening for comment in self.cycle_comments: self.sf.write("* {}\n".format(comment)) + # Trigger on the clk of the appropriate cycle trig_name = "clk" targ_name = "{0}".format("d[{0}]".format(self.probe_data)) trig_val = targ_val = 0.5 * self.vdd - # add measure statments for delay0 - # delay the target to measure after the negative edge + + # Delay the target to measure after the negative edge stimuli.gen_meas_delay(stim_file=self.sf, meas_name="DELAY0", trig_name=trig_name, @@ -207,11 +211,13 @@ class delay(): t_final=t_final) def find_feasible_period(self, load, slew): - """Uses an initial period and finds a feasible period before we + """ + Uses an initial period and finds a feasible period before we run the binary search algorithm to find min period. We check if the given clock period is valid and if it's not, we continue to double the period until we find a valid period to use as a - starting point. """ + starting point. + """ feasible_period = tech.spice["feasible_period"] time_out = 8 @@ -227,13 +233,19 @@ class delay(): feasible_period = 2 * feasible_period continue - debug.info(1, "Found feasible_period: {0}ns feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period,feasible_delay1,feasible_delay0,feasible_slew1,feasible_slew0)) + debug.info(1, "Found feasible_period: {0}ns feasible_delay1/0 {1}ns/{2}ns slew {3}ns/{4}ns".format(feasible_period, + feasible_delay1, + feasible_delay0, + feasible_slew1, + feasible_slew0)) return (feasible_period, feasible_delay1, feasible_delay0) def run_simulation(self, period, load, slew): - """ This tries to simulate a period and checks if the result - works. If so, it returns True and the delays and slews.""" + """ + This tries to simulate a period and checks if the result + works. If so, it returns True and the delays and slews. + """ # Checking from not data_value to data_value self.write_stimulus(period, load, slew) @@ -245,17 +257,37 @@ class delay(): # if it failed or the read was longer than a period if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float: - debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1)) + debug.info(2,"Failed simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period, + load, + slew, + delay0, + delay1, + slew0, + slew1)) return (False,0,0,0,0) + # Scale delays to ns (they previously could have not been floats) delay0 *= 1e9 delay1 *= 1e9 slew0 *= 1e9 slew1 *= 1e9 if delay0>period or delay1>period or slew0>period or slew1>period: - debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1)) + debug.info(2,"UNsuccessful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period, + load, + slew, + delay0, + delay1, + slew0, + slew1)) return (False,0,0,0,0) else: - debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period,load,slew,delay0,delay1,slew0,slew1)) + debug.info(2,"Successful simulation: period {0} load {1} slew {2}, delay0={3}n delay1={4}ns slew0={5}n slew1={6}n".format(period, + load, + slew, + delay0, + delay1, + slew0, + slew1)) + # For debug, you sometimes want to inspect each simulation. #key=raw_input("press return to continue") # The delay is from the negative edge for our SRAM @@ -264,8 +296,10 @@ class delay(): def find_min_period(self,feasible_period, load, slew, feasible_delay1, feasible_delay0): - """Searches for the smallest period with output delays being within 5% of - long period. """ + """ + Searches for the smallest period with output delays being within 5% of + long period. + """ previous_period = ub_period = feasible_period lb_period = 0.0 @@ -293,8 +327,10 @@ class delay(): def try_period(self, period, load, slew, feasible_delay1, feasible_delay0): - """ This tries to simulate a period and checks if the result - works. If it does and the delay is within 5% still, it returns True.""" + """ + This tries to simulate a period and checks if the result + works. If it does and the delay is within 5% still, it returns True. + """ # Checking from not data_value to data_value self.write_stimulus(period,load,slew) @@ -305,14 +341,22 @@ class delay(): slew1 = ch.convert_to_float(ch.parse_output("timing", "slew1")) # if it failed or the read was longer than a period if type(delay0)!=float or type(delay1)!=float or type(slew1)!=float or type(slew0)!=float: - debug.info(2,"Invalid measures: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1)) + debug.info(2,"Invalid measures: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, + delay0, + delay1, + slew0, + slew1)) return False delay0 *= 1e9 delay1 *= 1e9 slew0 *= 1e9 slew1 *= 1e9 if delay0>period or delay1>period or slew0>period or slew1>period: - debug.info(2,"Too long delay/slew: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1)) + debug.info(2,"Too long delay/slew: Period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, + delay0, + delay1, + slew0, + slew1)) return False else: if not ch.relative_compare(delay1,feasible_delay1,error_tolerance=0.05): @@ -325,7 +369,11 @@ class delay(): #key=raw_input("press return to continue") - debug.info(2,"Successful period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, delay0, delay1, slew0, slew1)) + debug.info(2,"Successful period {0}, delay0={1}ns, delay1={2}ns slew0={3}ns slew1={4}ns".format(period, + delay0, + delay1, + slew0, + slew1)) return True def set_probe(self,probe_address, probe_data): @@ -404,54 +452,95 @@ class delay(): and does not need a rising edge.""" self.cycle_comments = [] - # idle cycle, no operation - t_current = period self.cycle_times = [] - # cycle0: W data 1 address 1111 to initialize cell to a value + t_current = 0 + + # idle cycle, no operation + msg = "Idle cycle (no clock)" + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(0, + t_current, + msg)) self.cycle_times.append(t_current) - self.cycle_comments.append("Cycle0 {}ns: W data 1 address 11..11 to initialize cell".format(t_current)) t_current += period - # cycle1: W data 0 address 1111 (to ensure a write of value works) + # One period + msg = "W data 1 address 11..11 to initialize cell" self.cycle_times.append(t_current) - self.write0_cycle=1 - self.cycle_comments.append("Cycle1 {}ns: W data 0 address 11..11 (to ensure a write of value works)".format(t_current)) + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) + t_current += period + + # One period + msg = "W data 0 address 11..11 (to ensure a write of value works)" + self.cycle_times.append(t_current) + self.write0_cycle=len(self.cycle_times)-1 + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) t_current += period - # cycle2: W data 1 address 0000 (to clear the data bus cap) + # One period + msg = "W data 1 address 00..00 (to clear bus caps)" self.cycle_times.append(t_current) - self.cycle_comments.append("Cycle2 {}ns: W data 1 address 00..00 (to clear bus caps)".format(t_current)) + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) t_current += period - # cycle3: R data 0 address 1111 to check W0 works + # One period + msg = "R data 0 address 11..11 to check W0 worked" self.cycle_times.append(t_current) - self.read0_cycle=3 - self.cycle_comments.append("Cycle3 {}ns: R data 0 address 11..11 to check W0 worked".format(t_current)) + self.read0_cycle=len(self.cycle_times)-1 + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) t_current += period - # cycle4: W data 1 address 1111 (to ensure a write of value works) + # One period + msg = "Idle cycle" + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) self.cycle_times.append(t_current) - self.write1_cycle=4 - self.cycle_comments.append("Cycle4 {}ns: W data 1 address 11..11 (to ensure a write of value worked)".format(t_current)) t_current += period - # cycle5: W data 0 address 0000 (to clear the data bus cap) + # One period + msg = "W data 1 address 11..11 (to ensure a write of value worked)" self.cycle_times.append(t_current) - self.cycle_comments.append("Cycle5 {}ns: W data 0 address 00..00 (to clear bus caps)".format(t_current)) + self.write1_cycle=len(self.cycle_times)-1 + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) + t_current += period + + # One period + msg = "W data 0 address 00..00 (to clear bus caps)" + self.cycle_times.append(t_current) + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) t_current += period - # cycle6: R data 1 address 1111 to check W1 works + # One period + msg = "R data 1 address 11..11 to check W1 worked" self.cycle_times.append(t_current) - self.read1_cycle=6 - self.cycle_comments.append("Cycle6 {}ns: R data 1 address 11..11 to check W1 worked".format(t_current)) + self.read1_cycle=len(self.cycle_times)-1 + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) t_current += period - # cycle7: wait a clock period to end the simulation + # One period + msg = "Idle cycle" + self.cycle_comments.append("Cycle{0}\t{1}ns:\t{2}".format(len(self.cycle_times)-1, + t_current, + msg)) self.cycle_times.append(t_current) - self.cycle_comments.append("Cycle7 {}ns: Idle period to end simulation".format(t_current)) t_current += period + def analytical_model(self,sram, slews, loads): """ Just return the analytical model results for the SRAM. """ @@ -480,3 +569,54 @@ class delay(): } return data + def gen_data(self, clk_times, sig_name, period, slew): + """ Generates the PWL data inputs for a simulation timing test. """ + # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP + # we are asserting the opposite value on the other side of the tx gate during + # the read to be "worst case". Otherwise, it can actually assist the read. + values = [0, 1, 0, 1, 1, 1, 1, 0, 0, 0 ] + stimuli.gen_pwl(self.sf, sig_name, clk_times, values, period, slew, 0.05) + + def gen_addr(self, clk_times, addr, period, slew): + """ + Generates the address inputs for a simulation timing test. + This alternates between all 1's and all 0's for the address. + """ + + zero_values = [0, 0, 0, 1, 0, 0, 0, 1, 0, 0 ] + ones_values = [1, 1, 1, 0, 1, 0, 1, 0, 1, 1 ] + + for i in range(len(addr)): + sig_name = "A[{0}]".format(i) + if addr[i]=="1": + stimuli.gen_pwl(self.sf, sig_name, clk_times, ones_values, period, slew, 0.05) + else: + stimuli.gen_pwl(self.sf, sig_name, clk_times, zero_values, period, slew, 0.05) + + + def gen_csb(self, clk_times, period, slew): + """ Generates the PWL CSb signal """ + # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP + # Keep CSb asserted in NOP for measuring >1 period + values = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0] + stimuli.gen_pwl(self.sf, "csb", clk_times, values, period, slew, 0.05) + + def gen_web(self, clk_times, period, slew): + """ Generates the PWL WEb signal """ + # values for NOP, W1, W0, W1, R0, NOP, W1, W0, R1, NOP + # Keep WEb deasserted in NOP for measuring >1 period + values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1] + stimuli.gen_pwl(self.sf, "web", clk_times, values, period, slew, 0.05) + + # Keep acc_en deasserted in NOP for measuring >1 period + values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1] + stimuli.gen_pwl(self.sf, "acc_en", clk_times, values, period, slew, 0) + values = [0, 1, 1, 1, 0, 0, 1, 1, 0, 0] + stimuli.gen_pwl(self.sf, "acc_en_inv", clk_times, values, period, slew, 0) + + def gen_oeb(self, clk_times, period, slew): + """ Generates the PWL WEb signal """ + # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP + # Keep OEb asserted in NOP for measuring >1 period + values = [1, 1, 1, 1, 0, 0, 1, 1, 0, 0] + stimuli.gen_pwl(self.sf, "oeb", clk_times, values, period, slew, 0.05) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index b2a87479..fb93a105 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -1,8 +1,5 @@ -import os -import sys -import re +import os,sys,re,shutil import debug -import tech import math import setup_hold import delay @@ -34,7 +31,9 @@ class lib: self.sram.word_size) else: # Else, use the non-reduced netlist file for simulation - self.sim_sp_file = self.sp_file + self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp) + # Make a copy in temp for debugging + shutil.copy(self.sp_file, self.sim_sp_file) # These are the parameters to determine the table sizes #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8]) diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index a184ffcb..f9c1161b 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -37,7 +37,7 @@ class setup_hold(): self.write_header(correct_value) # instantiate the master-slave d-flip-flop - self.sf.write("* Instantiation of the Master-Slave D-flip-flop\n") + self.sf.write("\n* Instantiation of the Master-Slave D-flip-flop\n") stimuli.inst_model(stim_file=self.sf, pins=self.pins, model_name=self.model_name) @@ -58,7 +58,7 @@ class setup_hold(): def write_header(self, correct_value): """ Write the header file with all the models and the power supplies. """ - self.sf.write("* Stimulus for setup/hold: data {0} period {1}n\n".format(correct_value, self.period)) + self.sf.write("\n* Stimulus for setup/hold: data {0} period {1}n\n".format(correct_value, self.period)) # include files in stimulus file self.model_list = tech.spice["fet_models"] + [self.model_location] @@ -66,7 +66,7 @@ class setup_hold(): models=self.model_list) # add vdd/gnd statements - self.sf.write("* Global Power Supplies\n") + self.sf.write("\n* Global Power Supplies\n") stimuli.write_supply(self.sf) @@ -76,7 +76,7 @@ class setup_hold(): characterization. """ - self.sf.write("* Generation of the data and clk signals\n") + self.sf.write("\n* Generation of the data and clk signals\n") incorrect_value = stimuli.get_inverse_value(correct_value) if mode=="HOLD": init_value = incorrect_value @@ -89,7 +89,7 @@ class setup_hold(): stimuli.gen_pwl(stim_file=self.sf, sig_name="data", - clk_times=[self.period, target_time], + clk_times=[0, self.period, target_time], data_values=[init_value, start_value, end_value], period=target_time, slew=self.constrained_input_slew, @@ -105,7 +105,7 @@ class setup_hold(): # without using .IC on an internal node. # Return input to value after one period. # The second pulse is the characterization one at 2*period - clk_times=[0.1*self.period,self.period,2*self.period], + clk_times=[0, 0.1*self.period,self.period,2*self.period], data_values=[0, 1, 0, 1], period=2*self.period, slew=self.constrained_input_slew, @@ -132,7 +132,7 @@ class setup_hold(): din_rise_or_fall = "RISE" - self.sf.write("* Measure statements for pass/fail verification\n") + self.sf.write("\n* Measure statements for pass/fail verification\n") trig_name = "clk" targ_name = "dout" trig_val = targ_val = 0.5 * self.vdd diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 7986f11e..b82d6aa7 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -1,7 +1,7 @@ """ -This file generates the test structure and stimulus for an sram -simulation. There are various functions that can be be used to -generate stimulus for other simulations as well. +This file generates simple spice cards for simulation. There are +various functions that can be be used to generate stimulus for other +simulations as well. """ import tech @@ -22,7 +22,7 @@ tx_width = tech.spice["minwidth_tx"] tx_length = tech.spice["channel"] def inst_sram(stim_file, abits, dbits, sram_name): - """function to instatiate the sram subckt""" + """ Function to instatiate an SRAM subckt. """ stim_file.write("Xsram ") for i in range(dbits): stim_file.write("D[{0}] ".format(i)) @@ -32,11 +32,11 @@ def inst_sram(stim_file, abits, dbits, sram_name): stim_file.write("{0} ".format(i)) stim_file.write("{0} ".format(tech.spice["clk"])) stim_file.write("{0} {1} ".format(vdd_name, gnd_name)) - stim_file.write("{0}\n\n".format(sram_name)) + stim_file.write("{0}\n".format(sram_name)) def inst_model(stim_file, pins, model_name): - """function to instantiate a model""" + """ Function to instantiate a generic model with a set of pins """ stim_file.write("X{0} ".format(model_name)) for pin in pins: stim_file.write("{0} ".format(pin)) @@ -44,7 +44,7 @@ def inst_model(stim_file, pins, model_name): def create_inverter(stim_file, size=1, beta=2.5): - """Generates inverter for the top level signals (only for sim purposes)""" + """ Generates inverter for the top level signals (only for sim purposes) """ stim_file.write(".SUBCKT test_inv in out {0} {1}\n".format(vdd_name, gnd_name)) stim_file.write("mpinv out in {0} {0} {1} w={2}u l={3}u\n".format(vdd_name, pmos_name, @@ -58,9 +58,10 @@ def create_inverter(stim_file, size=1, beta=2.5): def create_buffer(stim_file, buffer_name, size=[1,3], beta=2.5): - """Generates buffer for top level signals (only for sim - purposes). Size is pair for PMOS, NMOS width multiple. It includes - a beta of 3.""" + """ + Generates buffer for top level signals (only for sim + purposes). Size is pair for PMOS, NMOS width multiple. + """ stim_file.write(".SUBCKT test_{2} in out {0} {1}\n".format(vdd_name, gnd_name, @@ -85,7 +86,7 @@ def create_buffer(stim_file, buffer_name, size=[1,3], beta=2.5): def inst_buffer(stim_file, buffer_name, signal_list): - """Adds buffers to each top level signal that is in signal_list (only for sim purposes)""" + """ Adds buffers to each top level signal that is in signal_list (only for sim purposes) """ for signal in signal_list: stim_file.write("X{0}_buffer {0} {0}_buf {1} {2} test_{3}\n".format(signal, "test"+vdd_name, @@ -94,7 +95,7 @@ def inst_buffer(stim_file, buffer_name, signal_list): def inst_inverter(stim_file, signal_list): - """Adds inv for each signal that needs its inverted version (only for sim purposes)""" + """ Adds inv for each signal that needs its inverted version (only for sim purposes) """ for signal in signal_list: stim_file.write("X{0}_inv {0} {0}_inv {1} {2} test_inv\n".format(signal, "test"+vdd_name, @@ -102,7 +103,7 @@ def inst_inverter(stim_file, signal_list): def inst_accesstx(stim_file, dbits): - """Adds transmission gate for inputs to data-bus (only for sim purposes)""" + """ Adds transmission gate for inputs to data-bus (only for sim purposes) """ stim_file.write("* Tx Pin-list: Drain Gate Source Body\n") for i in range(dbits): pmos_access_string="mp{0} DATA[{0}] acc_en D[{0}] {1} {2} w={3}u l={4}u\n" @@ -119,8 +120,11 @@ def inst_accesstx(stim_file, dbits): tx_length)) def gen_pulse(stim_file, sig_name, v1=gnd_voltage, v2=vdd_voltage, offset=0, period=1, t_rise=0, t_fall=0): - """Generates a periodic signal with 50% duty cycle and slew rates. Period is measured - from 50% to 50%.""" + """ + Generates a periodic signal with 50% duty cycle and slew rates. Period is measured + from 50% to 50%. + """ + stim_file.write("* PULSE: period={0}\n".format(period)) pulse_string="V{0} {0} 0 PULSE ({1} {2} {3}n {4}n {5}n {6}n {7}n)\n" stim_file.write(pulse_string.format(sig_name, v1, @@ -133,74 +137,32 @@ def gen_pulse(stim_file, sig_name, v1=gnd_voltage, v2=vdd_voltage, offset=0, per def gen_pwl(stim_file, sig_name, clk_times, data_values, period, slew, setup): + """ + Generate a PWL stimulus given a signal name and data values at each period. + Automatically creates slews and ensures each data occurs a setup before the clock + edge. The first clk_time should be 0 and is the initial time that corresponds + to the initial value. + """ # the initial value is not a clock time - debug.check(len(clk_times)+1==len(data_values),"Clock and data value lengths don't match.") + debug.check(len(clk_times)==len(data_values),"Clock and data value lengths don't match.") + # shift signal times earlier for setup time times = np.array(clk_times) - setup*period values = np.array(data_values) * vdd_voltage half_slew = 0.5 * slew + stim_file.write("* (time, data): {}\n".format(zip(clk_times, data_values))) stim_file.write("V{0} {0} 0 PWL (0n {1}v ".format(sig_name, values[0])) - for i in range(len(times)): + for i in range(1,len(times)): stim_file.write("{0}n {1}v {2}n {3}v ".format(times[i]-half_slew, - values[i], + values[i-1], times[i]+half_slew, - values[i+1])) + values[i])) stim_file.write(")\n") -def gen_data(stim_file, clk_times, sig_name, period, slew): - """Generates the PWL data inputs for a simulation timing test.""" - # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP - # we are asserting the opposite value on the other side of the tx gate during - # the read to be "worst case". Otherwise, it can actually assist the read. - values = [0, 1, 0, 1, 1, 1, 0, 0, 0 ] - gen_pwl(stim_file, sig_name, clk_times, values, period, slew, 0.05) - - -def gen_addr(stim_file, clk_times, addr, period, slew): - """Generates the address inputs for a simulation timing test. - One cycle is different to clear the bus - """ - - zero_values = [0, 0, 0, 1, 0, 0, 1, 0, 0 ] - ones_values = [1, 1, 1, 0, 1, 1, 0, 1, 1 ] - - for i in range(len(addr)): - sig_name = "A[{0}]".format(i) - if addr[i]=="1": - gen_pwl(stim_file, sig_name, clk_times, ones_values, period, slew, 0.05) - else: - gen_pwl(stim_file, sig_name, clk_times, zero_values, period, slew, 0.05) - def gen_constant(stim_file, sig_name, v_val): - """Generates a constant signal with reference voltage and the voltage value""" + """ Generates a constant signal with reference voltage and the voltage value """ stim_file.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val)) -def gen_csb(stim_file, clk_times, period, slew): - """ Generates the PWL CSb signal""" - # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP - values = [1, 0, 0, 0, 0, 0, 0, 0, 1] - gen_pwl(stim_file, "csb", clk_times, values, period, slew, 0.05) - -def gen_web(stim_file, clk_times, period, slew): - """ Generates the PWL WEb signal""" - # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP - values = [1, 0, 0, 0, 1, 0, 0, 1, 1] - gen_pwl(stim_file, "web", clk_times, values, period, slew, 0.05) - - values = [1, 0, 0, 0, 1, 0, 0, 1, 1] - gen_pwl(stim_file, "acc_en", clk_times, values, period, slew, 0) - values = [0, 1, 1, 1, 0, 1, 1, 0, 0] - gen_pwl(stim_file, "acc_en_inv", clk_times, values, period, slew, 0) - -def gen_oeb(stim_file, clk_times, period, slew): - """ Generates the PWL WEb signal""" - # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP - values = [1, 1, 1, 1, 0, 1, 1, 0, 1] - gen_pwl(stim_file, "oeb", clk_times, values, period, slew, 0.05) - - - - def get_inverse_voltage(value): if value > 0.5*vdd_voltage: return gnd_voltage @@ -219,7 +181,7 @@ def get_inverse_value(value): def gen_meas_delay(stim_file, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td): - """Creates the .meas statement for the measurement of delay""" + """ Creates the .meas statement for the measurement of delay """ measure_string=".meas tran {0} TRIG v({1}) VAL={2} {3}=1 TD={4}n TARG v({5}) VAL={6} {7}=1 TD={8}n\n\n" stim_file.write(measure_string.format(meas_name, trig_name, @@ -232,7 +194,7 @@ def gen_meas_delay(stim_file, meas_name, trig_name, targ_name, trig_val, targ_va targ_td)) def gen_meas_power(stim_file, meas_name, t_initial, t_final): - """Creates the .meas statement for the measurement of avg power""" + """ Creates the .meas statement for the measurement of avg power """ # power mea cmd is different in different spice: if OPTS.spice_name == "hspice": power_exp = "power" @@ -242,14 +204,16 @@ def gen_meas_power(stim_file, meas_name, t_initial, t_final): power_exp, t_initial, t_final)) - stim_file.write("\n") def write_control(stim_file, end_time): + """ Write the control cards to run and end the simulation """ # UIC is needed for ngspice to converge stim_file.write(".TRAN 5p {0}n UIC\n".format(end_time)) if OPTS.spice_name == "ngspice": # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method + # Do not remove this or it may not converge due to some "pa_00" nodes + # unless you figure out what these are. stim_file.write(".OPTIONS POST=1 RUNLVL=4 PROBE method=gear\n") else: stim_file.write(".OPTIONS POST=1 RUNLVL=4 PROBE\n") @@ -273,22 +237,22 @@ def write_include(stim_file, models): """Writes include statements, inputs are lists of model files""" for item in list(models): if os.path.isfile(item): - stim_file.write(".include \"{0}\"\n\n".format(item)) + stim_file.write(".include \"{0}\"\n".format(item)) else: debug.error("Could not find spice model: {0}\nSet SPICE_MODEL_DIR to over-ride path.\n".format(item)) def write_supply(stim_file): - """Writes supply voltage statements""" + """ Writes supply voltage statements """ stim_file.write("V{0} {0} 0.0 {1}\n".format(vdd_name, vdd_voltage)) stim_file.write("V{0} {0} 0.0 {1}\n".format(gnd_name, gnd_voltage)) # This is for the test power supply stim_file.write("V{0} {0} 0.0 {1}\n".format("test"+vdd_name, vdd_voltage)) - stim_file.write("V{0} {0} 0.0 {1}\n\n".format("test"+gnd_name, gnd_voltage)) + stim_file.write("V{0} {0} 0.0 {1}\n".format("test"+gnd_name, gnd_voltage)) def run_sim(): - """Run hspice in batch mode and output rawfile to parse.""" + """ Run hspice in batch mode and output rawfile to parse. """ temp_stim = "{0}stim.sp".format(OPTS.openram_temp) import datetime start_time = datetime.datetime.now() diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py index f53ac184..ead653b9 100644 --- a/compiler/characterizer/trim_spice.py +++ b/compiler/characterizer/trim_spice.py @@ -75,7 +75,8 @@ class trim_spice(): self.remove_insts("bitcell_array",[wl_name,bl_name]) # 2. Keep sense amps basd on BL - self.remove_insts("sense_amp_array",[bl_name]) + # FIXME: The bit lines are not indexed the same in sense_amp_array + #self.remove_insts("sense_amp_array",[bl_name]) # 3. Keep column muxes basd on BL self.remove_insts("column_mux_array",[bl_name]) diff --git a/compiler/control_logic.py b/compiler/control_logic.py index 7a1e3851..1ffe5aa5 100644 --- a/compiler/control_logic.py +++ b/compiler/control_logic.py @@ -68,7 +68,10 @@ class control_logic(design.design): c = reload(__import__(OPTS.replica_bitline)) replica_bitline = getattr(c, OPTS.replica_bitline) - self.replica_bitline = replica_bitline(rows=int(math.ceil(self.num_rows / 10.0))) + # FIXME: These should be tuned according to the size! + FO4_stages = 4 + bitcell_loads = int(math.ceil(self.num_rows / 10.0)) + self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads) self.add_mod(self.replica_bitline) diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index fb8ede4c..6be7dc77 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -10,12 +10,12 @@ from globals import OPTS class replica_bitline(design.design): """ - Generate a module that simulate the delay of control logic - and bit line charging. - Used for memory timing control + Generate a module that simulates the delay of control logic + and bit line charging. Stages is the depth of the FO4 delay + line and rows is the height of the replica bit loads. """ - def __init__(self, rows, name="replica_bitline"): + def __init__(self, FO4_stages, bitcell_loads, name="replica_bitline"): design.design.__init__(self, name) g = reload(__import__(OPTS.delay_chain)) @@ -29,7 +29,8 @@ class replica_bitline(design.design): for pin in ["en", "out", "vdd", "gnd"]: self.add_pin(pin) - self.rows = rows + self.bitcell_loads = bitcell_loads + self.FO4_stages = FO4_stages self.create_modules() self.calculate_module_offsets() @@ -78,10 +79,11 @@ class replica_bitline(design.design): self.add_mod(self.bitcell) # This is the replica bitline load column that is the height of our array - self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.rows) + self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads) self.add_mod(self.rbl) - - self.delay_chain = self.mod_delay_chain([1, 1, 1]) + + # FIXME: The FO and depth of this should be tuned + self.delay_chain = self.mod_delay_chain([4]*self.FO4_stages) self.add_mod(self.delay_chain) self.inv = pinv() @@ -123,7 +125,7 @@ class replica_bitline(design.design): self.rbl_inst=self.add_inst(name="load", mod=self.rbl, offset=self.rbl_offset) - self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.rows + ["vdd", "gnd"]) + self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.bitcell_loads + ["vdd", "gnd"]) @@ -239,12 +241,22 @@ class replica_bitline(design.design): def route_gnd(self): """ Route all signals connected to gnd """ - # Add a rail in M1 from bottom to two along delay chain - gnd_start = self.rbl_inv_inst.get_pin("gnd").bc() + gnd_start = self.rbl_inv_inst.get_pin("gnd").bc() gnd_end = vector(gnd_start.x, self.rbl_inst.uy()+2*self.m2_pitch) + + # Add a rail in M1 from bottom of delay chain to two above the RBL + # This prevents DRC errors with vias for the WL + dc_top = self.dc_inst.ur() + self.add_segment_center(layer="metal1", + start=vector(gnd_start.x, dc_top.y), + end=gnd_end) + + # Add a rail in M2 from RBL inverter to two above the RBL self.add_segment_center(layer="metal2", start=gnd_start, end=gnd_end) + + # Add pin from bottom to RBL inverter self.add_layout_pin_center_segment(text="gnd", layer="metal1", start=gnd_start.scale(1,0), @@ -252,7 +264,7 @@ class replica_bitline(design.design): # Connect the WL pins directly to gnd gnd_pin = self.get_pin("gnd").rc() - for row in range(self.rows): + for row in range(self.bitcell_loads): wl = "wl[{}]".format(row) pin = self.rbl_inst.get_pin(wl) start = vector(gnd_pin.x,pin.cy()) diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index d54878d7..36dd63e9 100644 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -21,10 +21,18 @@ class replica_bitline_test(openram_test): import replica_bitline - debug.info(2, "Testing RBL") - a = replica_bitline.replica_bitline(13) + stages=4 + rows=13 + debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) + a = replica_bitline.replica_bitline(stages,rows) self.local_check(a) + stages=8 + rows=100 + debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) + a = replica_bitline.replica_bitline(stages,rows) + self.local_check(a) + OPTS.check_lvsdrc = True globals.end_openram() diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index ebdc9093..aa9212b3 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -48,26 +48,27 @@ class timing_sram_test(openram_test): loads = [tech.spice["FF_in_cap"]*4] slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) + #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.0339194, - 'read0_power': 0.0340617, - 'write0_power': 0.0287779, - 'delay1': [0.0575725], - 'delay0': [0.16744839999999997], - 'min_period': 0.391, - 'write1_power': 0.0299736, - 'slew0': [0.026416], - 'slew1': [0.020441199999999996]} + golden_data = {'read1_power': 0.0345742, + 'read0_power': 0.03526189999999999, + 'write0_power': 0.0270014, + 'delay1': [0.0573107], + 'delay0': [0.07055809999999998], + 'min_period': 0.234, + 'write1_power': 0.0376625, + 'slew0': [0.0284344], + 'slew1': [0.0189185]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 5.557800000000001, - 'read0_power': 5.5712, - 'write0_power': 3.8325, - 'delay1': [1.0323], - 'delay0': [2.2134], - 'min_period': 6.25, - 'write1_power': 3.6903, - 'slew0': [1.3009000000000002], - 'slew1': [0.983561]} + golden_data = {'read1_power': 11.2474, + 'read0_power': 11.3148, + 'write0_power': 6.9064, + 'delay1': [1.0298], + 'delay0': [1.4102], + 'min_period': 4.063, + 'write1_power': 11.6964, + 'slew0': [1.3118], + 'slew1': [0.9816656]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index ccf40f31..be2c04d6 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -46,26 +46,27 @@ class timing_sram_test(openram_test): loads = [tech.spice["FF_in_cap"]*4] slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data,slews,loads) + #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': 0.03228762, - 'read0_power': 0.03281849, - 'write0_power': 0.02902607, - 'delay1': [0.059081419999999996], - 'delay0': [0.1716648], - 'min_period': 0.391, - 'write1_power': 0.02879424, - 'slew0': [0.02851539], - 'slew1': [0.02319674]} + golden_data = {'read1_power': 0.03308298, + 'read0_power': 0.03866541, + 'write0_power': 0.02695139, + 'delay1': [0.05840294000000001], + 'delay0': [0.40787249999999997], + 'min_period': 0.781, + 'write1_power': 0.037257830000000006, + 'slew0': [0.035826199999999996], + 'slew1': [0.02059459]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': 5.063901, - 'read0_power': 4.926464999999999, - 'write0_power': 3.480712, - 'delay1': [1.044746], - 'delay0': [2.23024], - 'min_period': 6.563, - 'write1_power': 3.1949449999999997, - 'slew0': [1.3469], - 'slew1': [1.035352]} + golden_data = {'read1_power': 10.31395, + 'read0_power': 10.0321, + 'write0_power': 6.072756, + 'delay1': [1.042564], + 'delay0': [1.412224], + 'min_period': 4.688, + 'write1_power': 10.53758, + 'slew0': [1.355812], + 'slew1': [1.03401]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 30392fa5..69288350 100644 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -20,8 +20,8 @@ class openram_test(openram_test): debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" - # make a temp directory for output - out_path = "/tmp/testsram" + # make a temp directory for output + out_path = "/tmp/testsram_{0}".format(OPTS.tech_name) # make sure we start without the files existing if os.path.exists(out_path): diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.lef b/compiler/tests/golden/sram_2_16_1_freepdk45.lef index 51d895b5..b2d656fe 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.lef +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.lef @@ -4165,6 +4165,7 @@ MACRO sram_2_16_1_freepdk45 RECT 750.0 30905.0 685.0 30970.0 ; RECT 32.5 30615.0 -32.5 31175.0 ; RECT 1377.5 30615.0 1312.5 31175.0 ; + RECT 1377.5 39337.5 1312.5 36955.0 ; RECT 1312.5 33907.5 1025.0 33972.5 ; RECT 1312.5 36317.5 1025.0 36382.5 ; RECT 1377.5 31862.5 935.0 31927.5 ; @@ -4209,11 +4210,11 @@ MACRO sram_2_16_1_freepdk45 RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33497.5 2465.0 33562.5 ; RECT 2330.0 33307.5 2465.0 33372.5 ; - RECT 1312.5 35352.5 1377.5 35417.5 ; - RECT 4002.5 35352.5 4067.5 35417.5 ; - RECT 1312.5 35255.0 1377.5 35385.0 ; - RECT 1345.0 35352.5 4035.0 35417.5 ; - RECT 4002.5 35255.0 4067.5 35385.0 ; + RECT 1312.5 39272.5 1377.5 39337.5 ; + RECT 4002.5 39272.5 4067.5 39337.5 ; + RECT 1312.5 39175.0 1377.5 39305.0 ; + RECT 1345.0 39272.5 4035.0 39337.5 ; + RECT 4002.5 39175.0 4067.5 39305.0 ; RECT 2875.0 34562.5 2690.0 34627.5 ; RECT 4035.0 34562.5 3850.0 34627.5 ; RECT 3917.5 34202.5 4067.5 34267.5 ; @@ -4255,6 +4256,279 @@ MACRO sram_2_16_1_freepdk45 RECT 2722.5 34695.0 2657.5 35255.0 ; RECT 4067.5 34695.0 4002.5 35255.0 ; RECT 3340.0 34820.0 3475.0 34885.0 ; + RECT 2875.0 35682.5 2690.0 35747.5 ; + RECT 4035.0 35682.5 3850.0 35747.5 ; + RECT 3917.5 35322.5 4067.5 35387.5 ; + RECT 3032.5 35322.5 2657.5 35387.5 ; + RECT 3917.5 35512.5 3032.5 35577.5 ; + RECT 3032.5 35322.5 2897.5 35387.5 ; + RECT 3032.5 35512.5 2897.5 35577.5 ; + RECT 3032.5 35512.5 2897.5 35577.5 ; + RECT 3032.5 35322.5 2897.5 35387.5 ; + RECT 3917.5 35322.5 3782.5 35387.5 ; + RECT 3917.5 35512.5 3782.5 35577.5 ; + RECT 3917.5 35512.5 3782.5 35577.5 ; + RECT 3917.5 35322.5 3782.5 35387.5 ; + RECT 2942.5 35682.5 2807.5 35747.5 ; + RECT 3917.5 35682.5 3782.5 35747.5 ; + RECT 3475.0 35380.0 3340.0 35445.0 ; + RECT 3475.0 35380.0 3340.0 35445.0 ; + RECT 3440.0 35545.0 3375.0 35610.0 ; + RECT 2722.5 35255.0 2657.5 35815.0 ; + RECT 4067.5 35255.0 4002.5 35815.0 ; + RECT 3340.0 35380.0 3475.0 35445.0 ; + RECT 2875.0 36242.5 2690.0 36307.5 ; + RECT 4035.0 36242.5 3850.0 36307.5 ; + RECT 3917.5 35882.5 4067.5 35947.5 ; + RECT 3032.5 35882.5 2657.5 35947.5 ; + RECT 3917.5 36072.5 3032.5 36137.5 ; + RECT 3032.5 35882.5 2897.5 35947.5 ; + RECT 3032.5 36072.5 2897.5 36137.5 ; + RECT 3032.5 36072.5 2897.5 36137.5 ; + RECT 3032.5 35882.5 2897.5 35947.5 ; + RECT 3917.5 35882.5 3782.5 35947.5 ; + RECT 3917.5 36072.5 3782.5 36137.5 ; + RECT 3917.5 36072.5 3782.5 36137.5 ; + RECT 3917.5 35882.5 3782.5 35947.5 ; + RECT 2942.5 36242.5 2807.5 36307.5 ; + RECT 3917.5 36242.5 3782.5 36307.5 ; + RECT 3475.0 35940.0 3340.0 36005.0 ; + RECT 3475.0 35940.0 3340.0 36005.0 ; + RECT 3440.0 36105.0 3375.0 36170.0 ; + RECT 2722.5 35815.0 2657.5 36375.0 ; + RECT 4067.5 35815.0 4002.5 36375.0 ; + RECT 3340.0 35940.0 3475.0 36005.0 ; + RECT 2875.0 36802.5 2690.0 36867.5 ; + RECT 4035.0 36802.5 3850.0 36867.5 ; + RECT 3917.5 36442.5 4067.5 36507.5 ; + RECT 3032.5 36442.5 2657.5 36507.5 ; + RECT 3917.5 36632.5 3032.5 36697.5 ; + RECT 3032.5 36442.5 2897.5 36507.5 ; + RECT 3032.5 36632.5 2897.5 36697.5 ; + RECT 3032.5 36632.5 2897.5 36697.5 ; + RECT 3032.5 36442.5 2897.5 36507.5 ; + RECT 3917.5 36442.5 3782.5 36507.5 ; + RECT 3917.5 36632.5 3782.5 36697.5 ; + RECT 3917.5 36632.5 3782.5 36697.5 ; + RECT 3917.5 36442.5 3782.5 36507.5 ; + RECT 2942.5 36802.5 2807.5 36867.5 ; + RECT 3917.5 36802.5 3782.5 36867.5 ; + RECT 3475.0 36500.0 3340.0 36565.0 ; + RECT 3475.0 36500.0 3340.0 36565.0 ; + RECT 3440.0 36665.0 3375.0 36730.0 ; + RECT 2722.5 36375.0 2657.5 36935.0 ; + RECT 4067.5 36375.0 4002.5 36935.0 ; + RECT 3340.0 36500.0 3475.0 36565.0 ; + RECT 2875.0 37362.5 2690.0 37427.5 ; + RECT 4035.0 37362.5 3850.0 37427.5 ; + RECT 3917.5 37002.5 4067.5 37067.5 ; + RECT 3032.5 37002.5 2657.5 37067.5 ; + RECT 3917.5 37192.5 3032.5 37257.5 ; + RECT 3032.5 37002.5 2897.5 37067.5 ; + RECT 3032.5 37192.5 2897.5 37257.5 ; + RECT 3032.5 37192.5 2897.5 37257.5 ; + RECT 3032.5 37002.5 2897.5 37067.5 ; + RECT 3917.5 37002.5 3782.5 37067.5 ; + RECT 3917.5 37192.5 3782.5 37257.5 ; + RECT 3917.5 37192.5 3782.5 37257.5 ; + RECT 3917.5 37002.5 3782.5 37067.5 ; + RECT 2942.5 37362.5 2807.5 37427.5 ; + RECT 3917.5 37362.5 3782.5 37427.5 ; + RECT 3475.0 37060.0 3340.0 37125.0 ; + RECT 3475.0 37060.0 3340.0 37125.0 ; + RECT 3440.0 37225.0 3375.0 37290.0 ; + RECT 2722.5 36935.0 2657.5 37495.0 ; + RECT 4067.5 36935.0 4002.5 37495.0 ; + RECT 3340.0 37060.0 3475.0 37125.0 ; + RECT 2875.0 37922.5 2690.0 37987.5 ; + RECT 4035.0 37922.5 3850.0 37987.5 ; + RECT 3917.5 37562.5 4067.5 37627.5 ; + RECT 3032.5 37562.5 2657.5 37627.5 ; + RECT 3917.5 37752.5 3032.5 37817.5 ; + RECT 3032.5 37562.5 2897.5 37627.5 ; + RECT 3032.5 37752.5 2897.5 37817.5 ; + RECT 3032.5 37752.5 2897.5 37817.5 ; + RECT 3032.5 37562.5 2897.5 37627.5 ; + RECT 3917.5 37562.5 3782.5 37627.5 ; + RECT 3917.5 37752.5 3782.5 37817.5 ; + RECT 3917.5 37752.5 3782.5 37817.5 ; + RECT 3917.5 37562.5 3782.5 37627.5 ; + RECT 2942.5 37922.5 2807.5 37987.5 ; + RECT 3917.5 37922.5 3782.5 37987.5 ; + RECT 3475.0 37620.0 3340.0 37685.0 ; + RECT 3475.0 37620.0 3340.0 37685.0 ; + RECT 3440.0 37785.0 3375.0 37850.0 ; + RECT 2722.5 37495.0 2657.5 38055.0 ; + RECT 4067.5 37495.0 4002.5 38055.0 ; + RECT 3340.0 37620.0 3475.0 37685.0 ; + RECT 2875.0 38482.5 2690.0 38547.5 ; + RECT 4035.0 38482.5 3850.0 38547.5 ; + RECT 3917.5 38122.5 4067.5 38187.5 ; + RECT 3032.5 38122.5 2657.5 38187.5 ; + RECT 3917.5 38312.5 3032.5 38377.5 ; + RECT 3032.5 38122.5 2897.5 38187.5 ; + RECT 3032.5 38312.5 2897.5 38377.5 ; + RECT 3032.5 38312.5 2897.5 38377.5 ; + RECT 3032.5 38122.5 2897.5 38187.5 ; + RECT 3917.5 38122.5 3782.5 38187.5 ; + RECT 3917.5 38312.5 3782.5 38377.5 ; + RECT 3917.5 38312.5 3782.5 38377.5 ; + RECT 3917.5 38122.5 3782.5 38187.5 ; + RECT 2942.5 38482.5 2807.5 38547.5 ; + RECT 3917.5 38482.5 3782.5 38547.5 ; + RECT 3475.0 38180.0 3340.0 38245.0 ; + RECT 3475.0 38180.0 3340.0 38245.0 ; + RECT 3440.0 38345.0 3375.0 38410.0 ; + RECT 2722.5 38055.0 2657.5 38615.0 ; + RECT 4067.5 38055.0 4002.5 38615.0 ; + RECT 3340.0 38180.0 3475.0 38245.0 ; + RECT 2875.0 39042.5 2690.0 39107.5 ; + RECT 4035.0 39042.5 3850.0 39107.5 ; + RECT 3917.5 38682.5 4067.5 38747.5 ; + RECT 3032.5 38682.5 2657.5 38747.5 ; + RECT 3917.5 38872.5 3032.5 38937.5 ; + RECT 3032.5 38682.5 2897.5 38747.5 ; + RECT 3032.5 38872.5 2897.5 38937.5 ; + RECT 3032.5 38872.5 2897.5 38937.5 ; + RECT 3032.5 38682.5 2897.5 38747.5 ; + RECT 3917.5 38682.5 3782.5 38747.5 ; + RECT 3917.5 38872.5 3782.5 38937.5 ; + RECT 3917.5 38872.5 3782.5 38937.5 ; + RECT 3917.5 38682.5 3782.5 38747.5 ; + RECT 2942.5 39042.5 2807.5 39107.5 ; + RECT 3917.5 39042.5 3782.5 39107.5 ; + RECT 3475.0 38740.0 3340.0 38805.0 ; + RECT 3475.0 38740.0 3340.0 38805.0 ; + RECT 3440.0 38905.0 3375.0 38970.0 ; + RECT 2722.5 38615.0 2657.5 39175.0 ; + RECT 4067.5 38615.0 4002.5 39175.0 ; + RECT 3340.0 38740.0 3475.0 38805.0 ; + RECT 2505.0 38187.5 2690.0 38122.5 ; + RECT 1345.0 38187.5 1530.0 38122.5 ; + RECT 1462.5 38547.5 1312.5 38482.5 ; + RECT 2347.5 38547.5 2722.5 38482.5 ; + RECT 1462.5 38357.5 2347.5 38292.5 ; + RECT 2347.5 38547.5 2482.5 38482.5 ; + RECT 2347.5 38357.5 2482.5 38292.5 ; + RECT 2347.5 38357.5 2482.5 38292.5 ; + RECT 2347.5 38547.5 2482.5 38482.5 ; + RECT 1462.5 38547.5 1597.5 38482.5 ; + RECT 1462.5 38357.5 1597.5 38292.5 ; + RECT 1462.5 38357.5 1597.5 38292.5 ; + RECT 1462.5 38547.5 1597.5 38482.5 ; + RECT 2437.5 38187.5 2572.5 38122.5 ; + RECT 1462.5 38187.5 1597.5 38122.5 ; + RECT 1905.0 38490.0 2040.0 38425.0 ; + RECT 1905.0 38490.0 2040.0 38425.0 ; + RECT 1940.0 38325.0 2005.0 38260.0 ; + RECT 2657.5 38615.0 2722.5 38055.0 ; + RECT 1312.5 38615.0 1377.5 38055.0 ; + RECT 1905.0 38425.0 2040.0 38490.0 ; + RECT 2505.0 37627.5 2690.0 37562.5 ; + RECT 1345.0 37627.5 1530.0 37562.5 ; + RECT 1462.5 37987.5 1312.5 37922.5 ; + RECT 2347.5 37987.5 2722.5 37922.5 ; + RECT 1462.5 37797.5 2347.5 37732.5 ; + RECT 2347.5 37987.5 2482.5 37922.5 ; + RECT 2347.5 37797.5 2482.5 37732.5 ; + RECT 2347.5 37797.5 2482.5 37732.5 ; + RECT 2347.5 37987.5 2482.5 37922.5 ; + RECT 1462.5 37987.5 1597.5 37922.5 ; + RECT 1462.5 37797.5 1597.5 37732.5 ; + RECT 1462.5 37797.5 1597.5 37732.5 ; + RECT 1462.5 37987.5 1597.5 37922.5 ; + RECT 2437.5 37627.5 2572.5 37562.5 ; + RECT 1462.5 37627.5 1597.5 37562.5 ; + RECT 1905.0 37930.0 2040.0 37865.0 ; + RECT 1905.0 37930.0 2040.0 37865.0 ; + RECT 1940.0 37765.0 2005.0 37700.0 ; + RECT 2657.5 38055.0 2722.5 37495.0 ; + RECT 1312.5 38055.0 1377.5 37495.0 ; + RECT 1905.0 37865.0 2040.0 37930.0 ; + RECT 2505.0 37067.5 2690.0 37002.5 ; + RECT 1345.0 37067.5 1530.0 37002.5 ; + RECT 1462.5 37427.5 1312.5 37362.5 ; + RECT 2347.5 37427.5 2722.5 37362.5 ; + RECT 1462.5 37237.5 2347.5 37172.5 ; + RECT 2347.5 37427.5 2482.5 37362.5 ; + RECT 2347.5 37237.5 2482.5 37172.5 ; + RECT 2347.5 37237.5 2482.5 37172.5 ; + RECT 2347.5 37427.5 2482.5 37362.5 ; + RECT 1462.5 37427.5 1597.5 37362.5 ; + RECT 1462.5 37237.5 1597.5 37172.5 ; + RECT 1462.5 37237.5 1597.5 37172.5 ; + RECT 1462.5 37427.5 1597.5 37362.5 ; + RECT 2437.5 37067.5 2572.5 37002.5 ; + RECT 1462.5 37067.5 1597.5 37002.5 ; + RECT 1905.0 37370.0 2040.0 37305.0 ; + RECT 1905.0 37370.0 2040.0 37305.0 ; + RECT 1940.0 37205.0 2005.0 37140.0 ; + RECT 2657.5 37495.0 2722.5 36935.0 ; + RECT 1312.5 37495.0 1377.5 36935.0 ; + RECT 1905.0 37305.0 2040.0 37370.0 ; + RECT 2505.0 36507.5 2690.0 36442.5 ; + RECT 1345.0 36507.5 1530.0 36442.5 ; + RECT 1462.5 36867.5 1312.5 36802.5 ; + RECT 2347.5 36867.5 2722.5 36802.5 ; + RECT 1462.5 36677.5 2347.5 36612.5 ; + RECT 2347.5 36867.5 2482.5 36802.5 ; + RECT 2347.5 36677.5 2482.5 36612.5 ; + RECT 2347.5 36677.5 2482.5 36612.5 ; + RECT 2347.5 36867.5 2482.5 36802.5 ; + RECT 1462.5 36867.5 1597.5 36802.5 ; + RECT 1462.5 36677.5 1597.5 36612.5 ; + RECT 1462.5 36677.5 1597.5 36612.5 ; + RECT 1462.5 36867.5 1597.5 36802.5 ; + RECT 2437.5 36507.5 2572.5 36442.5 ; + RECT 1462.5 36507.5 1597.5 36442.5 ; + RECT 1905.0 36810.0 2040.0 36745.0 ; + RECT 1905.0 36810.0 2040.0 36745.0 ; + RECT 1940.0 36645.0 2005.0 36580.0 ; + RECT 2657.5 36935.0 2722.5 36375.0 ; + RECT 1312.5 36935.0 1377.5 36375.0 ; + RECT 1905.0 36745.0 2040.0 36810.0 ; + RECT 2505.0 35947.5 2690.0 35882.5 ; + RECT 1345.0 35947.5 1530.0 35882.5 ; + RECT 1462.5 36307.5 1312.5 36242.5 ; + RECT 2347.5 36307.5 2722.5 36242.5 ; + RECT 1462.5 36117.5 2347.5 36052.5 ; + RECT 2347.5 36307.5 2482.5 36242.5 ; + RECT 2347.5 36117.5 2482.5 36052.5 ; + RECT 2347.5 36117.5 2482.5 36052.5 ; + RECT 2347.5 36307.5 2482.5 36242.5 ; + RECT 1462.5 36307.5 1597.5 36242.5 ; + RECT 1462.5 36117.5 1597.5 36052.5 ; + RECT 1462.5 36117.5 1597.5 36052.5 ; + RECT 1462.5 36307.5 1597.5 36242.5 ; + RECT 2437.5 35947.5 2572.5 35882.5 ; + RECT 1462.5 35947.5 1597.5 35882.5 ; + RECT 1905.0 36250.0 2040.0 36185.0 ; + RECT 1905.0 36250.0 2040.0 36185.0 ; + RECT 1940.0 36085.0 2005.0 36020.0 ; + RECT 2657.5 36375.0 2722.5 35815.0 ; + RECT 1312.5 36375.0 1377.5 35815.0 ; + RECT 1905.0 36185.0 2040.0 36250.0 ; + RECT 2505.0 35387.5 2690.0 35322.5 ; + RECT 1345.0 35387.5 1530.0 35322.5 ; + RECT 1462.5 35747.5 1312.5 35682.5 ; + RECT 2347.5 35747.5 2722.5 35682.5 ; + RECT 1462.5 35557.5 2347.5 35492.5 ; + RECT 2347.5 35747.5 2482.5 35682.5 ; + RECT 2347.5 35557.5 2482.5 35492.5 ; + RECT 2347.5 35557.5 2482.5 35492.5 ; + RECT 2347.5 35747.5 2482.5 35682.5 ; + RECT 1462.5 35747.5 1597.5 35682.5 ; + RECT 1462.5 35557.5 1597.5 35492.5 ; + RECT 1462.5 35557.5 1597.5 35492.5 ; + RECT 1462.5 35747.5 1597.5 35682.5 ; + RECT 2437.5 35387.5 2572.5 35322.5 ; + RECT 1462.5 35387.5 1597.5 35322.5 ; + RECT 1905.0 35690.0 2040.0 35625.0 ; + RECT 1905.0 35690.0 2040.0 35625.0 ; + RECT 1940.0 35525.0 2005.0 35460.0 ; + RECT 2657.5 35815.0 2722.5 35255.0 ; + RECT 1312.5 35815.0 1377.5 35255.0 ; + RECT 1905.0 35625.0 2040.0 35690.0 ; RECT 2505.0 34827.5 2690.0 34762.5 ; RECT 1345.0 34827.5 1530.0 34762.5 ; RECT 1462.5 35187.5 1312.5 35122.5 ; @@ -4298,13 +4572,14 @@ MACRO sram_2_16_1_freepdk45 RECT 1312.5 34695.0 1377.5 34135.0 ; RECT 1905.0 34505.0 2040.0 34570.0 ; RECT 3340.0 34425.0 3475.0 34490.0 ; - RECT 3340.0 34985.0 3475.0 35050.0 ; - RECT 1905.0 34900.0 2040.0 34965.0 ; + RECT 3340.0 36665.0 3475.0 36730.0 ; + RECT 3340.0 38905.0 3475.0 38970.0 ; + RECT 1905.0 36580.0 2040.0 36645.0 ; RECT 3340.0 34260.0 3475.0 34325.0 ; RECT 1940.0 34135.0 2005.0 34340.0 ; - RECT 2657.5 34135.0 2722.5 35255.0 ; - RECT 1312.5 34135.0 1377.5 35255.0 ; - RECT 4002.5 34135.0 4067.5 35255.0 ; + RECT 2657.5 34135.0 2722.5 39175.0 ; + RECT 1312.5 34135.0 1377.5 39175.0 ; + RECT 4002.5 34135.0 4067.5 39175.0 ; RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ; @@ -5170,18 +5445,45 @@ MACRO sram_2_16_1_freepdk45 RECT 1207.5 32062.5 1137.5 32660.0 ; RECT 785.0 32062.5 715.0 32342.5 ; RECT 3372.5 34457.5 3442.5 34852.5 ; - RECT 2655.0 34982.5 2725.0 35052.5 ; - RECT 2655.0 35062.5 2725.0 35132.5 ; - RECT 2690.0 34982.5 3407.5 35052.5 ; - RECT 2655.0 35017.5 2725.0 35097.5 ; - RECT 1972.5 35062.5 2690.0 35132.5 ; - RECT 1937.5 34537.5 2007.5 34932.5 ; + RECT 3372.5 34852.5 3442.5 35412.5 ; + RECT 3372.5 35412.5 3442.5 35972.5 ; + RECT 3372.5 35972.5 3442.5 36532.5 ; + RECT 3372.5 36697.5 3442.5 37092.5 ; + RECT 3372.5 37092.5 3442.5 37652.5 ; + RECT 3372.5 37652.5 3442.5 38212.5 ; + RECT 3372.5 38212.5 3442.5 38772.5 ; + RECT 2655.0 38902.5 2725.0 38972.5 ; + RECT 2655.0 38422.5 2725.0 38492.5 ; + RECT 2690.0 38902.5 3407.5 38972.5 ; + RECT 2655.0 38457.5 2725.0 38937.5 ; + RECT 1972.5 38422.5 2690.0 38492.5 ; + RECT 1937.5 37897.5 2007.5 38457.5 ; + RECT 1937.5 37337.5 2007.5 37897.5 ; + RECT 1937.5 36777.5 2007.5 37337.5 ; + RECT 1937.5 36217.5 2007.5 36612.5 ; + RECT 1937.5 35657.5 2007.5 36217.5 ; + RECT 1937.5 35097.5 2007.5 35657.5 ; + RECT 1937.5 34537.5 2007.5 35097.5 ; RECT 3340.0 34817.5 3475.0 34887.5 ; + RECT 3340.0 35377.5 3475.0 35447.5 ; + RECT 3340.0 35937.5 3475.0 36007.5 ; + RECT 3340.0 36497.5 3475.0 36567.5 ; + RECT 3340.0 37057.5 3475.0 37127.5 ; + RECT 3340.0 37617.5 3475.0 37687.5 ; + RECT 3340.0 38177.5 3475.0 38247.5 ; + RECT 3340.0 38737.5 3475.0 38807.5 ; + RECT 1905.0 38422.5 2040.0 38492.5 ; + RECT 1905.0 37862.5 2040.0 37932.5 ; + RECT 1905.0 37302.5 2040.0 37372.5 ; + RECT 1905.0 36742.5 2040.0 36812.5 ; + RECT 1905.0 36182.5 2040.0 36252.5 ; + RECT 1905.0 35622.5 2040.0 35692.5 ; RECT 1905.0 35062.5 2040.0 35132.5 ; RECT 1905.0 34502.5 2040.0 34572.5 ; RECT 3340.0 34422.5 3475.0 34492.5 ; - RECT 3340.0 34982.5 3475.0 35052.5 ; - RECT 1905.0 34897.5 2040.0 34967.5 ; + RECT 3340.0 36662.5 3475.0 36732.5 ; + RECT 3340.0 38902.5 3475.0 38972.5 ; + RECT 1905.0 36577.5 2040.0 36647.5 ; RECT 935.0 33800.0 225.0 32455.0 ; RECT 935.0 33800.0 230.0 35145.0 ; RECT 935.0 36490.0 230.0 35145.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.lib b/compiler/tests/golden/sram_2_16_1_freepdk45.lib index 7b56503b..5bae0bc7 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.032264359"); + values("0.04024341"); } fall_power(scalar){ - values("0.033266382"); + values("0.029869287"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.039765915"); + values("0.050563718"); } fall_power(scalar){ - values("0.039839075"); + values("0.055867096"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.055, 0.056, 0.064",\ - "0.056, 0.057, 0.064",\ - "0.061, 0.062, 0.07"); + values("0.055, 0.056, 0.063",\ + "0.056, 0.057, 0.063",\ + "0.061, 0.062, 0.069"); } cell_fall(CELL_TABLE) { - values("0.17, 0.171, 0.179",\ - "0.171, 0.172, 0.18",\ - "0.176, 0.177, 0.185"); + values("0.442, 0.443, 0.452",\ + "0.442, 0.443, 0.453",\ + "0.448, 0.449, 0.458"); } rise_transition(CELL_TABLE) { - values("0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028"); + values("0.013, 0.015, 0.026",\ + "0.013, 0.015, 0.026",\ + "0.013, 0.015, 0.026"); } fall_transition(CELL_TABLE) { - values("0.019, 0.02, 0.035",\ - "0.019, 0.02, 0.035",\ - "0.019, 0.02, 0.035"); + values("0.029, 0.031, 0.044",\ + "0.029, 0.031, 0.044",\ + "0.029, 0.031, 0.044"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.2345"); + values("0.449"); } fall_constraint(scalar) { - values("0.2345"); + values("0.449"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("0.469"); + values("0.898"); } fall_constraint(scalar) { - values("0.469"); + values("0.898"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib index 990f264e..e0360805 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.043273977"); + values("0.0370166"); } fall_power(scalar){ - values("0.042322667"); + values("0.026622831"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.088241812"); + values("0.034203045"); } fall_power(scalar){ - values("0.088188668"); + values("0.039377859"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.055, 0.055, 0.063",\ - "0.055, 0.056, 0.063",\ - "0.061, 0.062, 0.069"); + values("0.054, 0.055, 0.061",\ + "0.055, 0.055, 0.062",\ + "0.06, 0.061, 0.067"); } cell_fall(CELL_TABLE) { - values("0.162, 0.163, 0.171",\ - "0.163, 0.164, 0.172",\ - "0.168, 0.169, 0.178"); + values("0.438, 0.439, 0.449",\ + "0.439, 0.44, 0.449",\ + "0.445, 0.446, 0.455"); } rise_transition(CELL_TABLE) { - values("0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028",\ - "0.015, 0.016, 0.028"); + values("0.013, 0.014, 0.026",\ + "0.013, 0.014, 0.026",\ + "0.013, 0.015, 0.026"); } fall_transition(CELL_TABLE) { - values("0.018, 0.02, 0.035",\ - "0.018, 0.02, 0.035",\ - "0.018, 0.02, 0.035"); + values("0.027, 0.029, 0.043",\ + "0.027, 0.029, 0.043",\ + "0.027, 0.029, 0.043"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.2245"); + values("0.449"); } fall_constraint(scalar) { - values("0.2245"); + values("0.449"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("0.449"); + values("0.898"); } fall_constraint(scalar) { - values("0.449"); + values("0.898"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef index 65c62604..7a2a54f2 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef @@ -4105,6 +4105,7 @@ MACRO sram_2_16_1_scn3me_subm RECT 16050.0 358350.0 15150.0 359250.0 ; RECT 8850.0 353400.0 7950.0 363000.0 ; RECT 22650.0 353400.0 21750.0 363000.0 ; + RECT 22650.0 499050.0 21750.0 430200.0 ; RECT 21750.0 397050.0 17400.0 397950.0 ; RECT 21750.0 420450.0 17400.0 421350.0 ; RECT 22650.0 371550.0 16800.0 372450.0 ; @@ -4149,11 +4150,11 @@ MACRO sram_2_16_1_scn3me_subm RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 398400.0 33750.0 399600.0 ; RECT 32550.0 396000.0 33750.0 397200.0 ; - RECT 21750.0 430950.0 22650.0 431850.0 ; - RECT 49350.0 430950.0 50250.0 431850.0 ; - RECT 21750.0 429600.0 22650.0 431400.0 ; - RECT 22200.0 430950.0 49800.0 431850.0 ; - RECT 49350.0 429600.0 50250.0 431400.0 ; + RECT 21750.0 498150.0 22650.0 499050.0 ; + RECT 49350.0 498150.0 50250.0 499050.0 ; + RECT 21750.0 496800.0 22650.0 498600.0 ; + RECT 22200.0 498150.0 49800.0 499050.0 ; + RECT 49350.0 496800.0 50250.0 498600.0 ; RECT 37950.0 417000.0 36000.0 418200.0 ; RECT 49800.0 417000.0 47850.0 418200.0 ; RECT 48450.0 412200.0 50250.0 413400.0 ; @@ -4195,6 +4196,279 @@ MACRO sram_2_16_1_scn3me_subm RECT 36450.0 420000.0 35550.0 429600.0 ; RECT 50250.0 420000.0 49350.0 429600.0 ; RECT 42600.0 422400.0 43800.0 423600.0 ; + RECT 37950.0 436200.0 36000.0 437400.0 ; + RECT 49800.0 436200.0 47850.0 437400.0 ; + RECT 48450.0 431400.0 50250.0 432600.0 ; + RECT 39150.0 431400.0 35550.0 432600.0 ; + RECT 48450.0 434100.0 39150.0 435000.0 ; + RECT 39150.0 431400.0 37950.0 432600.0 ; + RECT 39150.0 433800.0 37950.0 435000.0 ; + RECT 39150.0 433800.0 37950.0 435000.0 ; + RECT 39150.0 431400.0 37950.0 432600.0 ; + RECT 48450.0 431400.0 47250.0 432600.0 ; + RECT 48450.0 433800.0 47250.0 435000.0 ; + RECT 48450.0 433800.0 47250.0 435000.0 ; + RECT 48450.0 431400.0 47250.0 432600.0 ; + RECT 38550.0 436200.0 37350.0 437400.0 ; + RECT 48450.0 436200.0 47250.0 437400.0 ; + RECT 43800.0 432000.0 42600.0 433200.0 ; + RECT 43800.0 432000.0 42600.0 433200.0 ; + RECT 43650.0 434550.0 42750.0 435450.0 ; + RECT 36450.0 429600.0 35550.0 439200.0 ; + RECT 50250.0 429600.0 49350.0 439200.0 ; + RECT 42600.0 432000.0 43800.0 433200.0 ; + RECT 37950.0 445800.0 36000.0 447000.0 ; + RECT 49800.0 445800.0 47850.0 447000.0 ; + RECT 48450.0 441000.0 50250.0 442200.0 ; + RECT 39150.0 441000.0 35550.0 442200.0 ; + RECT 48450.0 443700.0 39150.0 444600.0 ; + RECT 39150.0 441000.0 37950.0 442200.0 ; + RECT 39150.0 443400.0 37950.0 444600.0 ; + RECT 39150.0 443400.0 37950.0 444600.0 ; + RECT 39150.0 441000.0 37950.0 442200.0 ; + RECT 48450.0 441000.0 47250.0 442200.0 ; + RECT 48450.0 443400.0 47250.0 444600.0 ; + RECT 48450.0 443400.0 47250.0 444600.0 ; + RECT 48450.0 441000.0 47250.0 442200.0 ; + RECT 38550.0 445800.0 37350.0 447000.0 ; + RECT 48450.0 445800.0 47250.0 447000.0 ; + RECT 43800.0 441600.0 42600.0 442800.0 ; + RECT 43800.0 441600.0 42600.0 442800.0 ; + RECT 43650.0 444150.0 42750.0 445050.0 ; + RECT 36450.0 439200.0 35550.0 448800.0 ; + RECT 50250.0 439200.0 49350.0 448800.0 ; + RECT 42600.0 441600.0 43800.0 442800.0 ; + RECT 37950.0 455400.0 36000.0 456600.0 ; + RECT 49800.0 455400.0 47850.0 456600.0 ; + RECT 48450.0 450600.0 50250.0 451800.0 ; + RECT 39150.0 450600.0 35550.0 451800.0 ; + RECT 48450.0 453300.0 39150.0 454200.0 ; + RECT 39150.0 450600.0 37950.0 451800.0 ; + RECT 39150.0 453000.0 37950.0 454200.0 ; + RECT 39150.0 453000.0 37950.0 454200.0 ; + RECT 39150.0 450600.0 37950.0 451800.0 ; + RECT 48450.0 450600.0 47250.0 451800.0 ; + RECT 48450.0 453000.0 47250.0 454200.0 ; + RECT 48450.0 453000.0 47250.0 454200.0 ; + RECT 48450.0 450600.0 47250.0 451800.0 ; + RECT 38550.0 455400.0 37350.0 456600.0 ; + RECT 48450.0 455400.0 47250.0 456600.0 ; + RECT 43800.0 451200.0 42600.0 452400.0 ; + RECT 43800.0 451200.0 42600.0 452400.0 ; + RECT 43650.0 453750.0 42750.0 454650.0 ; + RECT 36450.0 448800.0 35550.0 458400.0 ; + RECT 50250.0 448800.0 49350.0 458400.0 ; + RECT 42600.0 451200.0 43800.0 452400.0 ; + RECT 37950.0 465000.0 36000.0 466200.0 ; + RECT 49800.0 465000.0 47850.0 466200.0 ; + RECT 48450.0 460200.0 50250.0 461400.0 ; + RECT 39150.0 460200.0 35550.0 461400.0 ; + RECT 48450.0 462900.0 39150.0 463800.0 ; + RECT 39150.0 460200.0 37950.0 461400.0 ; + RECT 39150.0 462600.0 37950.0 463800.0 ; + RECT 39150.0 462600.0 37950.0 463800.0 ; + RECT 39150.0 460200.0 37950.0 461400.0 ; + RECT 48450.0 460200.0 47250.0 461400.0 ; + RECT 48450.0 462600.0 47250.0 463800.0 ; + RECT 48450.0 462600.0 47250.0 463800.0 ; + RECT 48450.0 460200.0 47250.0 461400.0 ; + RECT 38550.0 465000.0 37350.0 466200.0 ; + RECT 48450.0 465000.0 47250.0 466200.0 ; + RECT 43800.0 460800.0 42600.0 462000.0 ; + RECT 43800.0 460800.0 42600.0 462000.0 ; + RECT 43650.0 463350.0 42750.0 464250.0 ; + RECT 36450.0 458400.0 35550.0 468000.0 ; + RECT 50250.0 458400.0 49350.0 468000.0 ; + RECT 42600.0 460800.0 43800.0 462000.0 ; + RECT 37950.0 474600.0 36000.0 475800.0 ; + RECT 49800.0 474600.0 47850.0 475800.0 ; + RECT 48450.0 469800.0 50250.0 471000.0 ; + RECT 39150.0 469800.0 35550.0 471000.0 ; + RECT 48450.0 472500.0 39150.0 473400.0 ; + RECT 39150.0 469800.0 37950.0 471000.0 ; + RECT 39150.0 472200.0 37950.0 473400.0 ; + RECT 39150.0 472200.0 37950.0 473400.0 ; + RECT 39150.0 469800.0 37950.0 471000.0 ; + RECT 48450.0 469800.0 47250.0 471000.0 ; + RECT 48450.0 472200.0 47250.0 473400.0 ; + RECT 48450.0 472200.0 47250.0 473400.0 ; + RECT 48450.0 469800.0 47250.0 471000.0 ; + RECT 38550.0 474600.0 37350.0 475800.0 ; + RECT 48450.0 474600.0 47250.0 475800.0 ; + RECT 43800.0 470400.0 42600.0 471600.0 ; + RECT 43800.0 470400.0 42600.0 471600.0 ; + RECT 43650.0 472950.0 42750.0 473850.0 ; + RECT 36450.0 468000.0 35550.0 477600.0 ; + RECT 50250.0 468000.0 49350.0 477600.0 ; + RECT 42600.0 470400.0 43800.0 471600.0 ; + RECT 37950.0 484200.0 36000.0 485400.0 ; + RECT 49800.0 484200.0 47850.0 485400.0 ; + RECT 48450.0 479400.0 50250.0 480600.0 ; + RECT 39150.0 479400.0 35550.0 480600.0 ; + RECT 48450.0 482100.0 39150.0 483000.0 ; + RECT 39150.0 479400.0 37950.0 480600.0 ; + RECT 39150.0 481800.0 37950.0 483000.0 ; + RECT 39150.0 481800.0 37950.0 483000.0 ; + RECT 39150.0 479400.0 37950.0 480600.0 ; + RECT 48450.0 479400.0 47250.0 480600.0 ; + RECT 48450.0 481800.0 47250.0 483000.0 ; + RECT 48450.0 481800.0 47250.0 483000.0 ; + RECT 48450.0 479400.0 47250.0 480600.0 ; + RECT 38550.0 484200.0 37350.0 485400.0 ; + RECT 48450.0 484200.0 47250.0 485400.0 ; + RECT 43800.0 480000.0 42600.0 481200.0 ; + RECT 43800.0 480000.0 42600.0 481200.0 ; + RECT 43650.0 482550.0 42750.0 483450.0 ; + RECT 36450.0 477600.0 35550.0 487200.0 ; + RECT 50250.0 477600.0 49350.0 487200.0 ; + RECT 42600.0 480000.0 43800.0 481200.0 ; + RECT 37950.0 493800.0 36000.0 495000.0 ; + RECT 49800.0 493800.0 47850.0 495000.0 ; + RECT 48450.0 489000.0 50250.0 490200.0 ; + RECT 39150.0 489000.0 35550.0 490200.0 ; + RECT 48450.0 491700.0 39150.0 492600.0 ; + RECT 39150.0 489000.0 37950.0 490200.0 ; + RECT 39150.0 491400.0 37950.0 492600.0 ; + RECT 39150.0 491400.0 37950.0 492600.0 ; + RECT 39150.0 489000.0 37950.0 490200.0 ; + RECT 48450.0 489000.0 47250.0 490200.0 ; + RECT 48450.0 491400.0 47250.0 492600.0 ; + RECT 48450.0 491400.0 47250.0 492600.0 ; + RECT 48450.0 489000.0 47250.0 490200.0 ; + RECT 38550.0 493800.0 37350.0 495000.0 ; + RECT 48450.0 493800.0 47250.0 495000.0 ; + RECT 43800.0 489600.0 42600.0 490800.0 ; + RECT 43800.0 489600.0 42600.0 490800.0 ; + RECT 43650.0 492150.0 42750.0 493050.0 ; + RECT 36450.0 487200.0 35550.0 496800.0 ; + RECT 50250.0 487200.0 49350.0 496800.0 ; + RECT 42600.0 489600.0 43800.0 490800.0 ; + RECT 34050.0 480600.0 36000.0 479400.0 ; + RECT 22200.0 480600.0 24150.0 479400.0 ; + RECT 23550.0 485400.0 21750.0 484200.0 ; + RECT 32850.0 485400.0 36450.0 484200.0 ; + RECT 23550.0 482700.0 32850.0 481800.0 ; + RECT 32850.0 485400.0 34050.0 484200.0 ; + RECT 32850.0 483000.0 34050.0 481800.0 ; + RECT 32850.0 483000.0 34050.0 481800.0 ; + RECT 32850.0 485400.0 34050.0 484200.0 ; + RECT 23550.0 485400.0 24750.0 484200.0 ; + RECT 23550.0 483000.0 24750.0 481800.0 ; + RECT 23550.0 483000.0 24750.0 481800.0 ; + RECT 23550.0 485400.0 24750.0 484200.0 ; + RECT 33450.0 480600.0 34650.0 479400.0 ; + RECT 23550.0 480600.0 24750.0 479400.0 ; + RECT 28200.0 484800.0 29400.0 483600.0 ; + RECT 28200.0 484800.0 29400.0 483600.0 ; + RECT 28350.0 482250.0 29250.0 481350.0 ; + RECT 35550.0 487200.0 36450.0 477600.0 ; + RECT 21750.0 487200.0 22650.0 477600.0 ; + RECT 28200.0 483600.0 29400.0 484800.0 ; + RECT 34050.0 471000.0 36000.0 469800.0 ; + RECT 22200.0 471000.0 24150.0 469800.0 ; + RECT 23550.0 475800.0 21750.0 474600.0 ; + RECT 32850.0 475800.0 36450.0 474600.0 ; + RECT 23550.0 473100.0 32850.0 472200.0 ; + RECT 32850.0 475800.0 34050.0 474600.0 ; + RECT 32850.0 473400.0 34050.0 472200.0 ; + RECT 32850.0 473400.0 34050.0 472200.0 ; + RECT 32850.0 475800.0 34050.0 474600.0 ; + RECT 23550.0 475800.0 24750.0 474600.0 ; + RECT 23550.0 473400.0 24750.0 472200.0 ; + RECT 23550.0 473400.0 24750.0 472200.0 ; + RECT 23550.0 475800.0 24750.0 474600.0 ; + RECT 33450.0 471000.0 34650.0 469800.0 ; + RECT 23550.0 471000.0 24750.0 469800.0 ; + RECT 28200.0 475200.0 29400.0 474000.0 ; + RECT 28200.0 475200.0 29400.0 474000.0 ; + RECT 28350.0 472650.0 29250.0 471750.0 ; + RECT 35550.0 477600.0 36450.0 468000.0 ; + RECT 21750.0 477600.0 22650.0 468000.0 ; + RECT 28200.0 474000.0 29400.0 475200.0 ; + RECT 34050.0 461400.0 36000.0 460200.0 ; + RECT 22200.0 461400.0 24150.0 460200.0 ; + RECT 23550.0 466200.0 21750.0 465000.0 ; + RECT 32850.0 466200.0 36450.0 465000.0 ; + RECT 23550.0 463500.0 32850.0 462600.0 ; + RECT 32850.0 466200.0 34050.0 465000.0 ; + RECT 32850.0 463800.0 34050.0 462600.0 ; + RECT 32850.0 463800.0 34050.0 462600.0 ; + RECT 32850.0 466200.0 34050.0 465000.0 ; + RECT 23550.0 466200.0 24750.0 465000.0 ; + RECT 23550.0 463800.0 24750.0 462600.0 ; + RECT 23550.0 463800.0 24750.0 462600.0 ; + RECT 23550.0 466200.0 24750.0 465000.0 ; + RECT 33450.0 461400.0 34650.0 460200.0 ; + RECT 23550.0 461400.0 24750.0 460200.0 ; + RECT 28200.0 465600.0 29400.0 464400.0 ; + RECT 28200.0 465600.0 29400.0 464400.0 ; + RECT 28350.0 463050.0 29250.0 462150.0 ; + RECT 35550.0 468000.0 36450.0 458400.0 ; + RECT 21750.0 468000.0 22650.0 458400.0 ; + RECT 28200.0 464400.0 29400.0 465600.0 ; + RECT 34050.0 451800.0 36000.0 450600.0 ; + RECT 22200.0 451800.0 24150.0 450600.0 ; + RECT 23550.0 456600.0 21750.0 455400.0 ; + RECT 32850.0 456600.0 36450.0 455400.0 ; + RECT 23550.0 453900.0 32850.0 453000.0 ; + RECT 32850.0 456600.0 34050.0 455400.0 ; + RECT 32850.0 454200.0 34050.0 453000.0 ; + RECT 32850.0 454200.0 34050.0 453000.0 ; + RECT 32850.0 456600.0 34050.0 455400.0 ; + RECT 23550.0 456600.0 24750.0 455400.0 ; + RECT 23550.0 454200.0 24750.0 453000.0 ; + RECT 23550.0 454200.0 24750.0 453000.0 ; + RECT 23550.0 456600.0 24750.0 455400.0 ; + RECT 33450.0 451800.0 34650.0 450600.0 ; + RECT 23550.0 451800.0 24750.0 450600.0 ; + RECT 28200.0 456000.0 29400.0 454800.0 ; + RECT 28200.0 456000.0 29400.0 454800.0 ; + RECT 28350.0 453450.0 29250.0 452550.0 ; + RECT 35550.0 458400.0 36450.0 448800.0 ; + RECT 21750.0 458400.0 22650.0 448800.0 ; + RECT 28200.0 454800.0 29400.0 456000.0 ; + RECT 34050.0 442200.0 36000.0 441000.0 ; + RECT 22200.0 442200.0 24150.0 441000.0 ; + RECT 23550.0 447000.0 21750.0 445800.0 ; + RECT 32850.0 447000.0 36450.0 445800.0 ; + RECT 23550.0 444300.0 32850.0 443400.0 ; + RECT 32850.0 447000.0 34050.0 445800.0 ; + RECT 32850.0 444600.0 34050.0 443400.0 ; + RECT 32850.0 444600.0 34050.0 443400.0 ; + RECT 32850.0 447000.0 34050.0 445800.0 ; + RECT 23550.0 447000.0 24750.0 445800.0 ; + RECT 23550.0 444600.0 24750.0 443400.0 ; + RECT 23550.0 444600.0 24750.0 443400.0 ; + RECT 23550.0 447000.0 24750.0 445800.0 ; + RECT 33450.0 442200.0 34650.0 441000.0 ; + RECT 23550.0 442200.0 24750.0 441000.0 ; + RECT 28200.0 446400.0 29400.0 445200.0 ; + RECT 28200.0 446400.0 29400.0 445200.0 ; + RECT 28350.0 443850.0 29250.0 442950.0 ; + RECT 35550.0 448800.0 36450.0 439200.0 ; + RECT 21750.0 448800.0 22650.0 439200.0 ; + RECT 28200.0 445200.0 29400.0 446400.0 ; + RECT 34050.0 432600.0 36000.0 431400.0 ; + RECT 22200.0 432600.0 24150.0 431400.0 ; + RECT 23550.0 437400.0 21750.0 436200.0 ; + RECT 32850.0 437400.0 36450.0 436200.0 ; + RECT 23550.0 434700.0 32850.0 433800.0 ; + RECT 32850.0 437400.0 34050.0 436200.0 ; + RECT 32850.0 435000.0 34050.0 433800.0 ; + RECT 32850.0 435000.0 34050.0 433800.0 ; + RECT 32850.0 437400.0 34050.0 436200.0 ; + RECT 23550.0 437400.0 24750.0 436200.0 ; + RECT 23550.0 435000.0 24750.0 433800.0 ; + RECT 23550.0 435000.0 24750.0 433800.0 ; + RECT 23550.0 437400.0 24750.0 436200.0 ; + RECT 33450.0 432600.0 34650.0 431400.0 ; + RECT 23550.0 432600.0 24750.0 431400.0 ; + RECT 28200.0 436800.0 29400.0 435600.0 ; + RECT 28200.0 436800.0 29400.0 435600.0 ; + RECT 28350.0 434250.0 29250.0 433350.0 ; + RECT 35550.0 439200.0 36450.0 429600.0 ; + RECT 21750.0 439200.0 22650.0 429600.0 ; + RECT 28200.0 435600.0 29400.0 436800.0 ; RECT 34050.0 423000.0 36000.0 421800.0 ; RECT 22200.0 423000.0 24150.0 421800.0 ; RECT 23550.0 427800.0 21750.0 426600.0 ; @@ -4238,13 +4512,14 @@ MACRO sram_2_16_1_scn3me_subm RECT 21750.0 420000.0 22650.0 410400.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ; - RECT 42600.0 424800.0 43800.0 426000.0 ; - RECT 28200.0 423600.0 29400.0 424800.0 ; + RECT 42600.0 453600.0 43800.0 454800.0 ; + RECT 42600.0 492000.0 43800.0 493200.0 ; + RECT 28200.0 452400.0 29400.0 453600.0 ; RECT 42600.0 412800.0 43800.0 414000.0 ; RECT 28350.0 410400.0 29250.0 414150.0 ; - RECT 35550.0 410400.0 36450.0 429600.0 ; - RECT 21750.0 410400.0 22650.0 429600.0 ; - RECT 49350.0 410400.0 50250.0 429600.0 ; + RECT 35550.0 410400.0 36450.0 496800.0 ; + RECT 21750.0 410400.0 22650.0 496800.0 ; + RECT 49350.0 410400.0 50250.0 496800.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ; @@ -5079,18 +5354,45 @@ MACRO sram_2_16_1_scn3me_subm RECT 20400.0 376200.0 19500.0 384300.0 ; RECT 13650.0 376200.0 12750.0 381000.0 ; RECT 42750.0 415800.0 43650.0 423000.0 ; - RECT 35550.0 424950.0 36450.0 425850.0 ; - RECT 35550.0 426150.0 36450.0 427050.0 ; - RECT 36000.0 424950.0 43200.0 425850.0 ; - RECT 35550.0 425400.0 36450.0 426600.0 ; - RECT 28800.0 426150.0 36000.0 427050.0 ; - RECT 28350.0 417000.0 29250.0 424200.0 ; + RECT 42750.0 423000.0 43650.0 432600.0 ; + RECT 42750.0 432600.0 43650.0 442200.0 ; + RECT 42750.0 442200.0 43650.0 451800.0 ; + RECT 42750.0 454200.0 43650.0 461400.0 ; + RECT 42750.0 461400.0 43650.0 471000.0 ; + RECT 42750.0 471000.0 43650.0 480600.0 ; + RECT 42750.0 480600.0 43650.0 490200.0 ; + RECT 35550.0 492150.0 36450.0 493050.0 ; + RECT 35550.0 483750.0 36450.0 484650.0 ; + RECT 36000.0 492150.0 43200.0 493050.0 ; + RECT 35550.0 484200.0 36450.0 492600.0 ; + RECT 28800.0 483750.0 36000.0 484650.0 ; + RECT 28350.0 474600.0 29250.0 484200.0 ; + RECT 28350.0 465000.0 29250.0 474600.0 ; + RECT 28350.0 455400.0 29250.0 465000.0 ; + RECT 28350.0 445800.0 29250.0 453000.0 ; + RECT 28350.0 436200.0 29250.0 445800.0 ; + RECT 28350.0 426600.0 29250.0 436200.0 ; + RECT 28350.0 417000.0 29250.0 426600.0 ; RECT 42600.0 422400.0 43800.0 423600.0 ; + RECT 42600.0 432000.0 43800.0 433200.0 ; + RECT 42600.0 441600.0 43800.0 442800.0 ; + RECT 42600.0 451200.0 43800.0 452400.0 ; + RECT 42600.0 460800.0 43800.0 462000.0 ; + RECT 42600.0 470400.0 43800.0 471600.0 ; + RECT 42600.0 480000.0 43800.0 481200.0 ; + RECT 42600.0 489600.0 43800.0 490800.0 ; + RECT 28200.0 483600.0 29400.0 484800.0 ; + RECT 28200.0 474000.0 29400.0 475200.0 ; + RECT 28200.0 464400.0 29400.0 465600.0 ; + RECT 28200.0 454800.0 29400.0 456000.0 ; + RECT 28200.0 445200.0 29400.0 446400.0 ; + RECT 28200.0 435600.0 29400.0 436800.0 ; RECT 28200.0 426000.0 29400.0 427200.0 ; RECT 28200.0 416400.0 29400.0 417600.0 ; RECT 42600.0 415200.0 43800.0 416400.0 ; - RECT 42600.0 424800.0 43800.0 426000.0 ; - RECT 28200.0 423600.0 29400.0 424800.0 ; + RECT 42600.0 453600.0 43800.0 454800.0 ; + RECT 42600.0 492000.0 43800.0 493200.0 ; + RECT 28200.0 452400.0 29400.0 453600.0 ; RECT 16800.0 395400.0 6600.0 381600.0 ; RECT 16800.0 395400.0 6600.0 409200.0 ; RECT 16800.0 423000.0 6600.0 409200.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib index 5e3c613c..40941598 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("3.8220424"); + values("6.0607574"); } fall_power(scalar){ - values("4.3085394"); + values("3.8016626"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("6.224058"); + values("6.8609238"); } fall_power(scalar){ - values("6.0499775"); + values("5.9579654"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.676, 0.761, 1.441",\ - "0.679, 0.763, 1.444",\ - "0.731, 0.813, 1.493"); + values("0.676, 0.761, 1.439",\ + "0.679, 0.763, 1.443",\ + "0.731, 0.813, 1.491"); } cell_fall(CELL_TABLE) { - values("1.689, 1.797, 2.773",\ - "1.693, 1.802, 2.778",\ - "1.747, 1.856, 2.831"); + values("0.866, 0.99, 1.98",\ + "0.868, 0.993, 1.985",\ + "0.92, 1.042, 2.034"); } rise_transition(CELL_TABLE) { - values("0.186, 0.335, 1.875",\ - "0.187, 0.337, 1.875",\ - "0.19, 0.34, 1.875"); + values("0.184, 0.333, 1.877",\ + "0.185, 0.334, 1.877",\ + "0.188, 0.337, 1.877"); } fall_transition(CELL_TABLE) { - values("0.235, 0.445, 2.457",\ - "0.235, 0.445, 2.457",\ - "0.235, 0.445, 2.457"); + values("0.363, 0.486, 2.459",\ + "0.367, 0.488, 2.459",\ + "0.37, 0.495, 2.46"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("4.6875"); + values("3.125"); } fall_constraint(scalar) { - values("4.6875"); + values("3.125"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("9.375"); + values("6.25"); } fall_constraint(scalar) { - values("9.375"); + values("6.25"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib index 088b7826..201f0467 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("3.9245536"); + values("5.5339993"); } fall_power(scalar){ - values("4.1029534"); + values("3.2697936"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("6.3714394"); + values("5.5897458"); } fall_power(scalar){ - values("6.2007335"); + values("5.460329"); } } timing(){ @@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.668, 0.753, 1.433",\ - "0.671, 0.756, 1.437",\ - "0.723, 0.805, 1.485"); + values("0.664, 0.748, 1.425",\ + "0.667, 0.75, 1.429",\ + "0.718, 0.8, 1.477"); } cell_fall(CELL_TABLE) { - values("1.697, 1.807, 2.782",\ - "1.702, 1.811, 2.787",\ - "1.756, 1.865, 2.839"); + values("0.857, 0.981, 1.971",\ + "0.859, 0.984, 1.976",\ + "0.911, 1.033, 2.025"); } rise_transition(CELL_TABLE) { - values("0.185, 0.334, 1.877",\ - "0.186, 0.336, 1.877",\ - "0.188, 0.339, 1.878"); + values("0.182, 0.331, 1.876",\ + "0.183, 0.333, 1.876",\ + "0.186, 0.336, 1.876"); } fall_transition(CELL_TABLE) { - values("0.235, 0.444, 2.457",\ - "0.234, 0.444, 2.457",\ - "0.234, 0.444, 2.456"); + values("0.361, 0.487, 2.459",\ + "0.365, 0.488, 2.459",\ + "0.369, 0.496, 2.459"); } } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("4.6875"); + values("3.125"); } fall_constraint(scalar) { - values("4.6875"); + values("3.125"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("9.375"); + values("6.25"); } fall_constraint(scalar) { - values("9.375"); + values("6.25"); } } }