From 299512eba29daefeafcc636838055a9542f86617 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Wed, 22 Mar 2023 18:56:52 -0700 Subject: [PATCH] standardize array tests --- ...plica_bitcell_array_bothrbl_1rw_1r_test.py | 11 ++--- ...plica_bitcell_array_dummies_1rw_1r_test.py | 9 ++--- ..._replica_bitcell_array_dummies_1rw_test.py | 5 +-- ...plica_bitcell_array_leftrbl_1rw_1r_test.py | 10 ++--- ..._replica_bitcell_array_leftrbl_1rw_test.py | 5 +-- ...replica_bitcell_array_norbl_1rw_1r_test.py | 9 ++--- ...ed_replica_bitcell_array_norbl_1rw_test.py | 5 +-- ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 10 ++--- ...replica_bitcell_array_rightrbl_1rw_test.py | 39 ++++++++++++++++++ ...plica_bitcell_array_bothrbl_1rw_1r_test.py | 11 ++--- ...plica_bitcell_array_dummies_1rw_1r_test.py | 9 ++--- ..._replica_bitcell_array_dummies_1rw_test.py | 4 +- ...plica_bitcell_array_leftrbl_1rw_1r_test.py | 10 ++--- ..._replica_bitcell_array_leftrbl_1rw_test.py | 4 +- ...replica_bitcell_array_norbl_1rw_1r_test.py | 9 ++--- ...14_replica_bitcell_array_norbl_1rw_test.py | 5 +-- ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 12 ++---- ...replica_bitcell_array_rightrbl_1rw_test.py | 39 ++++++++++++++++++ .../15_local_bitcell_array_1rw_1r_test.py | 10 ++--- ...local_bitcell_array_bothrbl_1rw_1r_test.py | 40 +++++++++++++++++++ ...local_bitcell_array_dummies_1rw_1r_test.py | 40 +++++++++++++++++++ ...15_local_bitcell_array_dummies_1rw_test.py | 40 +++++++++++++++++++ ...local_bitcell_array_leftrbl_1rw_1r_test.py | 39 ++++++++++++++++++ ...15_local_bitcell_array_leftrbl_1rw_test.py | 40 +++++++++++++++++++ ...5_local_bitcell_array_norbl_1rw_1r_test.py | 40 +++++++++++++++++++ .../15_local_bitcell_array_norbl_1rw_test.py | 40 +++++++++++++++++++ ...ocal_bitcell_array_rightrbl_1rw_1r_test.py | 39 ++++++++++++++++++ ...5_local_bitcell_array_rightrbl_1rw_test.py | 40 +++++++++++++++++++ 28 files changed, 484 insertions(+), 90 deletions(-) create mode 100755 compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py create mode 100755 compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_dummies_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_norbl_1rw_test.py create mode 100755 compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py create mode 100755 compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py diff --git a/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py index a2f57e45..2237a21f 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_bothrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,13 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 array left and right replica for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0], - right_rbl=[1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with both replica columns") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py index bc432c6b..f361b4af 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_dummies_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py index 175689c3..6ce8a1c0 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_dummies_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py index 3e1bd805..72bc698c 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with left replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py index b4ba91d1..5d1523ae 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py index e9a61609..c1ea6516 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_norbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[0, 0]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index e845d32b..5eb5f98e 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_test(openram_test): +class capped_replica_bitcell_array_norbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class capped_replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py index deac7075..22433884 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class capped_replica_bitcell_array_1rw_1r_test(openram_test): +class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="capped_replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - right_rbl=[1]) + debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with right replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..bd654d73 --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column") + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py index d6e075a4..504e0390 100755 --- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_bothrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,13 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 array left and right replica for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0], - right_rbl=[1]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with both replica columns") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py index ebdc9584..13e0169a 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_dummies_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py index e893c3ca..465260b4 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_dummies_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_w_ports = 0 factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index 36254cb5..d4b514df 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,12 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - left_rbl=[0]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with left replica column") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py index f77a571d..9127a934 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_leftrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_w_ports = 0 factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py index 78f77ece..d2869183 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_norbl_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 non-replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[0, 0]) + debug.info(2, "Testing 4x4 replica array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index df20a19a..bc292041 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -14,7 +14,7 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_test(openram_test): +class replica_bitcell_array_norbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,8 +24,7 @@ class replica_bitcell_array_test(openram_test): OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - factory.reset() - debug.info(2, "Testing 4x4 array for bitcell") + debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py index 8d1d8f23..c2f29c2f 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -14,23 +14,19 @@ from openram.sram_factory import factory from openram import OPTS -class replica_bitcell_array_1rw_1r_test(openram_test): +class replica_bitcell_array_rightrbl_1rw_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 + OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 left replica array for dp cell") - a = factory.create(module_type="replica_bitcell_array", - cols=4, - rows=4, - rbl=[1, 1], - right_rbl=[1]) + debug.info(2, "Testing 7x5 replica array for 1rw cell with right replica column") + a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) self.local_check(a) openram.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..18ccb00c --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column") + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index b80342eb..8f9cebc0 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -28,23 +28,23 @@ class local_bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 openram.setup_bitcell() - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica columns or dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell without replica columns or dummy rows") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica column but with dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with dummy rows only") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with left replica column and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with left replica column") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with right replica column and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with right replica column") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) self.local_check(a) - debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with both replica columns and dummy rows") + debug.info(2, "Testing 4x4 local array for 1rw1r cell with both replica columns") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) self.local_check(a) diff --git a/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py new file mode 100755 index 00000000..08e4c5ee --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_bothrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with both replica columns") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py new file mode 100755 index 00000000..80667466 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_dummies_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with dummy rows only") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py b/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py new file mode 100755 index 00000000..20d2398e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_dummies_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_dummies_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with dummy row only") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py new file mode 100755 index 00000000..0e1f2918 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_leftrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with left replica column") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py new file mode 100755 index 00000000..756da97e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_leftrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with left replica column") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py new file mode 100755 index 00000000..f86188c2 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_norbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell without replica columns or dummy rows") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py new file mode 100755 index 00000000..795fd14e --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_norbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_norbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell without replica column or dummy row") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[0, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py new file mode 100755 index 00000000..88c0099d --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py @@ -0,0 +1,39 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_rightrbl_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with right replica column") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py new file mode 100755 index 00000000..b8427d82 --- /dev/null +++ b/compiler/tests/15_local_bitcell_array_rightrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class local_bitcell_array_rightrbl_1rw_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with right replica column") + a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())