From 2991534d3f2de86e6986cec02daa22523172de7b Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 23 Jul 2020 17:15:39 -0700 Subject: [PATCH] Drafting local bitline stuff. --- compiler/modules/local_bitcell_array.py | 33 +++++++++-------- compiler/modules/wordline_buffer_array.py | 6 ++-- compiler/tests/05_local_bitcell_array_test.py | 36 +++++++++++++++++++ 3 files changed, 58 insertions(+), 17 deletions(-) create mode 100755 compiler/tests/05_local_bitcell_array_test.py diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index fc3137c6..8b56ea19 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -13,12 +13,12 @@ from sram_factory import factory class local_bitcell_array(bitcell_base_array): """ - A local wordline array is a bitcell array with a wordline driver. + A local bitcell array is a bitcell array with a wordline driver. This can either be a single aray on its own if there is no hierarchical WL or it can be combined into a larger array with hierarchical WL. """ def __init__(self, name, rows, cols): - super().__init__(name, rows, cols) + super().__init__(name=name, rows=rows, cols=cols, column_offset=0) self.create_netlist() if not OPTS.netlist_only: @@ -36,7 +36,7 @@ class local_bitcell_array(bitcell_base_array): def create_layout(self): - self.place_array("bit_r{0}_c{1}") + self.place() self.add_layout_pins() @@ -46,21 +46,26 @@ class local_bitcell_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.bit_array = factory.create(module_type="bitcell_array", - rows=self.rows, - cols=self.cols, - column_offset=self.column_offset) - self.add_mod(self.bit_array) + # This is just used for names + self.cell = factory.create(module_type="bitcell") + + self.bitcell_array = factory.create(module_type="bitcell_array", + rows=self.row_size, + cols=self.column_size) + self.add_mod(self.bitcell_array) - self.wl_array = factory.create(module_type="wordline_driver_array", - rows=self.rows, - cols=self.cols) + self.wl_array = factory.create(module_type="wordline_buffer_array", + rows=self.row_size, + cols=self.column_size) self.add_mod(self.wl_array) def create_instances(self): """ Create the module instances used in this design """ - self.bitcell_inst = self.add_inst(mod=self.bitcell_array) - self.connect_inst(self.get_bitcell_pins(row, col)) - self.wl_inst = self.add_inst(mod=self.wl_array) + self.array_inst = self.add_inst(mod=self.bitcell_array) + self.connect_inst(self.pins) + + #wl_names = self.get_ + self.wl_inst = self.add_inst(mod=self.wl_array, + offset=self.bitcell_inst.lr()) self.connect_inst(self.get_bitcell_pins(row, col)) diff --git a/compiler/modules/wordline_buffer_array.py b/compiler/modules/wordline_buffer_array.py index 7dad327d..be0fe1f7 100644 --- a/compiler/modules/wordline_buffer_array.py +++ b/compiler/modules/wordline_buffer_array.py @@ -53,7 +53,7 @@ class wordline_buffer_array(design.design): self.add_pin("in_{0}".format(i), "INPUT") # Outputs from wordline_driver. for i in range(self.rows): - self.add_pin("wl_{0}".format(i), "OUTPUT") + self.add_pin("out_{0}".format(i), "OUTPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -100,7 +100,7 @@ class wordline_buffer_array(design.design): self.wld_inst.append(self.add_inst(name="wld{0}".format(row), mod=self.wl_driver)) self.connect_inst(["in_{0}".format(row), - "wl_{0}".format(row), + "out_{0}".format(row), "vdd", "gnd"]) def place_drivers(self): @@ -131,7 +131,7 @@ class wordline_buffer_array(design.design): # output each WL on the right wl_offset = inst.get_pin("Z").rc() - self.add_layout_pin_segment_center(text="wl_{0}".format(row), + self.add_layout_pin_segment_center(text="out_{0}".format(row), layer=self.route_layer, start=wl_offset, end=wl_offset - vector(self.m1_width, 0)) diff --git a/compiler/tests/05_local_bitcell_array_test.py b/compiler/tests/05_local_bitcell_array_test.py new file mode 100755 index 00000000..1a717fb2 --- /dev/null +++ b/compiler/tests/05_local_bitcell_array_test.py @@ -0,0 +1,36 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class local_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + + debug.info(2, "Testing 4x4 local bitcell array for 6t_cell") + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())