From 2954f13294a77cb154a971276c4cbac133c05673 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 14 Dec 2020 14:18:18 -0800 Subject: [PATCH] Update temp file to be relative --- compiler/base/hierarchy_design.py | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index e776ac3c..ee5e2653 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -52,10 +52,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): # Do not run if disabled in options. elif (OPTS.inline_lvsdrc or force_check or final_verification): - tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) - self.lvs_write(tempspice) - tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) - self.gds_write(tempgds) + tempspice = "{}.sp".format(self.name) + self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + tempgds = "{}.gds".format(self.name) + self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) # Final verification option does not allow nets to be connected by label. self.drc_errors = verify.run_drc(self.cell_name, tempgds, tempspice, extract=True, final_verification=final_verification) self.lvs_errors = verify.run_lvs(self.cell_name, tempgds, tempspice, final_verification=final_verification) @@ -81,10 +81,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if OPTS.netlist_only: return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - tempspice = "{0}{1}.sp".format(OPTS.openram_temp, self.name) - self.lvs_write(tempspice) - tempgds = "{0}{1}.gds".format(OPTS.openram_temp, self.cell_name) - self.gds_write(tempgds) + tempspice = "{}.sp".format(self.name) + self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + tempgds = "{}.gds".format(self.cell_name) + self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) num_errors = verify.run_drc(self.cell_name, tempgds, tempspice, final_verification=final_verification) debug.check(num_errors == 0, "DRC failed for {0} with {1} error(s)".format(self.cell_name, @@ -101,10 +101,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): if OPTS.netlist_only: return elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): - tempspice = "{0}{1}.sp".format(OPTS.openram_temp, self.cell_name) - self.lvs_write(tempspice) - tempgds = "{0}{1}.gds".format(OPTS.openram_temp, self.name) - self.gds_write(tempgds) + tempspice = "{}.sp".format(self.cell_name) + self.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice)) + tempgds = "{}.gds".format(self.name) + self.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) debug.check(num_errors == 0, "LVS failed for {0} with {1} error(s)".format(self.cell_name,