From 2948b08e6604e0bbf198014df99e2b70b5cc251a Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 6 Feb 2023 20:04:54 -0800 Subject: [PATCH] copy rbl default values logic from lower array modules --- compiler/modules/local_bitcell_array.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index e72a9d6e..f52248b2 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -30,9 +30,19 @@ class local_bitcell_array(bitcell_base_array): self.rows = rows self.cols = cols + # This is how many RBLs are in all the arrays self.rbl = rbl - self.left_rbl = left_rbl - self.right_rbl = right_rbl + # This specifies which RBL to put on the left or right by port number + # This could be an empty list + if left_rbl is not None: + self.left_rbl = left_rbl + else: + self.left_rbl = [] + # This could be an empty list + if right_rbl is not None: + self.right_rbl = right_rbl + else: + self.right_rbl=[] debug.check(len(self.all_ports) < 3, "Local bitcell array only supports dual port or less.")