diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index 861ea6be..a006068c 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -69,9 +69,10 @@ class control_logic(design.design):
         c = reload(__import__(OPTS.replica_bitline))
         replica_bitline = getattr(c, OPTS.replica_bitline)
         # FIXME: These should be tuned according to the size!
-        FO4_stages = 6
+        delay_stages = 4 # This should be even so that the delay line is inverting!
+        delay_fanout = 3
         bitcell_loads = int(math.ceil(self.num_rows / 5.0))
-        self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads)
+        self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads)
         self.add_mod(self.replica_bitline)
 
 
diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py
index b05da7ee..894b6dfb 100644
--- a/compiler/modules/delay_chain.py
+++ b/compiler/modules/delay_chain.py
@@ -20,6 +20,9 @@ class delay_chain(design.design):
         # and there should be functions to get 
         # area efficient inverter stage list 
 
+        for f in fanout_list:
+            debug.check(f>0,"Must have non-zero fanouts for each stage.")
+
         # number of inverters including any fanout loads.
         self.fanout_list = fanout_list
         self.num_inverters = 1 + sum(fanout_list)
diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py
index 6be7dc77..394e4c18 100644
--- a/compiler/modules/replica_bitline.py
+++ b/compiler/modules/replica_bitline.py
@@ -11,11 +11,11 @@ from globals import OPTS
 class replica_bitline(design.design):
     """
     Generate a module that simulates the delay of control logic 
-    and bit line charging. Stages is the depth of the FO4 delay
+    and bit line charging. Stages is the depth of the delay
     line and rows is the height of the replica bit loads.
     """
 
-    def __init__(self, FO4_stages, bitcell_loads, name="replica_bitline"):
+    def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
         design.design.__init__(self, name)
 
         g = reload(__import__(OPTS.delay_chain))
@@ -30,7 +30,8 @@ class replica_bitline(design.design):
         for pin in ["en", "out", "vdd", "gnd"]:
             self.add_pin(pin)
         self.bitcell_loads = bitcell_loads
-        self.FO4_stages = FO4_stages
+        self.delay_stages = delay_stages
+        self.delay_fanout = delay_fanout
 
         self.create_modules()
         self.calculate_module_offsets()
@@ -83,7 +84,7 @@ class replica_bitline(design.design):
         self.add_mod(self.rbl)
 
         # FIXME: The FO and depth of this should be tuned
-        self.delay_chain = self.mod_delay_chain([4]*self.FO4_stages)
+        self.delay_chain = self.mod_delay_chain([self.delay_fanout]*self.delay_stages)
         self.add_mod(self.delay_chain)
 
         self.inv = pinv()