From 2760beae341a736ac26ecd30b2308f3357c71836 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 21 Jun 2021 15:22:31 -0700 Subject: [PATCH] swap sky130 replica bitcell array power bias routing --- compiler/modules/bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 0e8b833f..8aa46b18 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -620,7 +620,7 @@ class bank(design.design): self.copy_power_pins(inst, "gnd", add_vias=False) if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: - for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']): + for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']): self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) # If we use the pinvbuf as the decoder, we need to add power pins.