diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 0e8b833f..8aa46b18 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -620,7 +620,7 @@ class bank(design.design):
             self.copy_power_pins(inst, "gnd", add_vias=False)
 
         if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
-            for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']):
+            for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']):
                 self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
 
         # If we use the pinvbuf as the decoder, we need to add power pins.