From 2709f61317255a8edd30d58c91ba7ffdde02fd5d Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 16 May 2023 14:38:51 -0700 Subject: [PATCH] fix index out of bounds bug --- compiler/modules/bank.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d3ca8e3a..561d68c3 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -865,8 +865,10 @@ class bank(design): driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] if self.has_rbl: driver_names = driver_names + ["rbl_wl"] - # rbl_wl in next two lines will be ignored by zip once driver_names is exhausted in the no rbl case - rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] + rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port] + else: + rbl_wl_name = None + # rbl_wl in next line will be ignored by zip once driver_names is exhausted in the no rbl case for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]): # The mid guarantees we exit the input cell to the right. driver_wl_pin = self.port_address_inst[port].get_pin(driver_name)