From 25bc3a66edc671098fa5a2a8de3f10fe575abedc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 17 Apr 2019 13:41:35 -0700 Subject: [PATCH] Add far left option for contact placement in pgates. --- compiler/base/contact.py | 2 +- compiler/bitcells/pbitcell.py | 8 ++++++-- compiler/bitcells/replica_pbitcell.py | 3 +-- compiler/pgates/pgate.py | 2 ++ compiler/pgates/pinv.py | 4 ++-- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/compiler/base/contact.py b/compiler/base/contact.py index f4b14d79..e7365ed9 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -185,7 +185,7 @@ from sram_factory import factory # This is not instantiated and used for calculations only. # These are static 1x1 contacts to reuse in all the design modules. well = factory.create(module_type="contact", layer_stack=("active", "contact", "metal1"), directions=("H","V")) -active = factory.create(module_type="contact", layer_stack=("active", "contact", "poly"), directions=("H","V")) +active = factory.create(module_type="contact", layer_stack=("active", "contact", "metal1"), directions=("H","V")) poly = factory.create(module_type="contact", layer_stack=("poly", "contact", "metal1"), directions=("V","H")) m1m2 = factory.create(module_type="contact", layer_stack=("metal1", "via1", "metal2"), directions=("H","V")) m2m3 = factory.create(module_type="contact", layer_stack=("metal2", "via2", "metal3"), directions=("V","H")) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index 552042f5..77ef295a 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -292,8 +292,12 @@ class pbitcell(design.design): self.add_path("poly", [self.inverter_nmos_right.get_pin("G").uc(), self.inverter_pmos_right.get_pin("G").bc()]) # connect output (drain/source) of inverters - self.add_path("metal1", [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()]) - self.add_path("metal1", [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()]) + self.add_path("metal1", + [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()], + width=contact.active.second_layer_width) + self.add_path("metal1", + [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()], + width=contact.active.second_layer_width) # add contacts to connect gate poly to drain/source metal1 (to connect Q to Q_bar) contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x + 0.5*contact.poly.height, self.cross_couple_upper_ypos) diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/bitcells/replica_pbitcell.py index 4d2ecd70..76687944 100644 --- a/compiler/bitcells/replica_pbitcell.py +++ b/compiler/bitcells/replica_pbitcell.py @@ -67,8 +67,7 @@ class replica_pbitcell(design.design): self.connect_inst(temp) def place_pbitcell(self): - offset = [0,0] - self.prbc_inst.place(offset=offset) + self.prbc_inst.place(offset=vector(0,0)) def route_rbc_connections(self): for port in range(self.total_ports): diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 25ea591f..073efa0c 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -74,6 +74,8 @@ class pgate(design.design): if position=="center": contact_offset = left_gate_offset + vector(0.5*self.poly_width, 0) + elif position=="farleft": + contact_offset = left_gate_offset - vector(0.5*contact.poly.width, 0) elif position=="left": contact_offset = left_gate_offset - vector(0.5*contact_width - 0.5*self.poly_width, 0) elif position=="right": diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 5f61d200..b488013d 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -58,7 +58,7 @@ class pinv(pgate.pgate): self.add_well_contacts() self.extend_wells(self.well_pos) self.connect_rails() - self.route_input_gate(self.pmos_inst, self.nmos_inst, self.output_pos.y, "A") + self.route_input_gate(self.pmos_inst, self.nmos_inst, self.output_pos.y, "A", position="farleft") self.route_outputs() def add_pins(self): @@ -222,7 +222,7 @@ class pinv(pgate.pgate): pmos_drain_pin = self.pmos_inst.get_pin("D") # Pick point at right most of NMOS and connect down to PMOS - nmos_drain_pos = nmos_drain_pin.lr() + nmos_drain_pos = nmos_drain_pin.bc() pmos_drain_pos = vector(nmos_drain_pos.x, pmos_drain_pin.uc().y) self.add_path("metal1",[nmos_drain_pos,pmos_drain_pos])