From 249b5355ba8ed083e011c000c3f3fb3ed6f8b01f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jun 2020 17:08:04 -0700 Subject: [PATCH] Adjust rbl route --- compiler/modules/bank.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 393631e5..2aa4e871 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -128,10 +128,10 @@ class bank(design.design): bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) # This will ensure the pin is only on the top or bottom edge if port % 2: - via_offset = bl_pin.uc() + vector(0, 1.5 * self.m2_pitch) + via_offset = bl_pin.uc() + vector(0, self.m2_pitch) left_right_offset = vector(self.max_x_offset, via_offset.y) else: - via_offset = bl_pin.bc() - vector(0, 1.5 * self.m2_pitch) + via_offset = bl_pin.bc() - vector(0, self.m2_pitch) left_right_offset = vector(self.min_x_offset, via_offset.y) self.add_via_stack_center(from_layer=bl_pin.layer, to_layer="m3",