From 242d90f543b53d7529053731581bb390492112cb Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Sat, 13 Aug 2022 13:58:53 -0700 Subject: [PATCH] Code format fixes --- compiler/modules/bank.py | 31 +++++-------------------------- compiler/modules/template.py | 12 ++++++------ 2 files changed, 11 insertions(+), 32 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 59a745b7..c9279d2a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -44,9 +44,6 @@ class bank(design): # The local control signals are gated when we have bank select logic, # so this prefix will be added to all of the input signals to create # the internal gated signals. - #if self.num_banks>1: - # self.prefix="gated_" - #else: self.prefix="" self.create_netlist() @@ -98,9 +95,6 @@ class bank(design): # For more than one bank, we have a bank select and name # the signals gated_*. - #if self.num_banks > 1: - # for port in self.all_ports: - # self.add_pin("bank_sel{}".format(port), "INPUT") for port in self.read_ports: self.add_pin("s_en{0}".format(port), "INPUT") for port in self.all_ports: @@ -128,8 +122,6 @@ class bank(design): self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) - #if self.num_banks > 1: - # self.route_bank_select(port) self.route_supplies() @@ -171,7 +163,6 @@ class bank(design): self.create_port_data() self.create_port_address() self.create_column_decoder() - #self.create_bank_select() def compute_instance_offsets(self): """ @@ -252,8 +243,6 @@ class bank(design): y_offset = min(self.column_decoder_offsets[port].y, self.port_data[port].column_mux_offset.y) else: y_offset = self.port_address_offsets[port].y - #if self.num_banks > 1: - # y_offset += self.bank_select.height + drc("well_to_well") self.bank_select_offsets[port] = vector(-x_offset, -y_offset) def compute_instance_port1_offsets(self): @@ -311,19 +300,18 @@ class bank(design): self.place_port_address(self.port_address_offsets) self.place_column_decoder(self.column_decoder_offsets) - #self.place_bank_select(self.bank_select_offsets) + # self.place_bank_select(self.bank_select_offsets) def compute_sizes(self): """ Computes the required sizes to create the bank """ - self.num_words_per_bank = self.num_words / self.num_banks self.num_bits_per_bank = self.word_size * self.num_words_per_bank self.num_cols = int(self.words_per_row * self.word_size) self.num_rows_temp = int(self.num_words_per_bank / self.words_per_row) self.num_rows = self.num_rows_temp + self.num_spare_rows - + self.row_addr_size = ceil(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size @@ -355,12 +343,8 @@ class bank(design): # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] for port in self.all_ports: - #if self.num_banks > 1: - # self.control_signals.append(["gated_" + str for str in self.input_control_signals[port]]) - #else: self.control_signals.append(self.input_control_signals[port]) - # The central bus is the column address (one hot) and row address (binary) if self.col_addr_size>0: self.num_col_addr_lines = 2**self.col_addr_size @@ -370,8 +354,8 @@ class bank(design): # Gap between decoder and array self.decoder_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 2 * self.m2_pitch, - drc("nwell_to_nwell")) + 2 * self.m2_pitch, + drc("nwell_to_nwell")) def add_modules(self): """ Add all the modules using the class loader """ @@ -409,9 +393,6 @@ class bank(design): port=port, bit_offsets=self.bit_offsets)) - #if(self.num_banks > 1): - # self.bank_select = factory.create(module_type="bank_select") - def create_bitcell_array(self): """ Creating Bitcell Array """ self.bitcell_array_inst=self.add_inst(name="bitcell_array", @@ -607,7 +588,7 @@ class bank(design): self.copy_layout_pin(inst, "gnd") if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: - for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']): + for pin_name, supply_name in zip(['vnb', 'vpb'], ['gnd', 'vdd']): self.copy_layout_pin(self.bitcell_array_inst, pin_name, new_name=supply_name) # If we use the pinvbuf as the decoder, we need to add power pins. @@ -688,7 +669,6 @@ class bank(design): names=self.control_signals[0], length=control_bus_length, vertical=True, - #make_pins=(self.num_banks==1), make_pins=(True), pitch=self.m3_pitch) @@ -706,7 +686,6 @@ class bank(design): names=list(reversed(self.control_signals[1])), length=control_bus_length, vertical=True, - #make_pins=(self.num_banks==1), make_pins=(True), pitch=self.m3_pitch) diff --git a/compiler/modules/template.py b/compiler/modules/template.py index 714833c0..ae93647f 100644 --- a/compiler/modules/template.py +++ b/compiler/modules/template.py @@ -66,12 +66,12 @@ class textSection(baseSection): self.text = text def expand(self, dict, fd): - varRE = re.compile('\{\{ (\S*) \}\}') + varRE = re.compile(r'\{\{ (\S*) \}\}') vars = varRE.finditer(self.text) newText = self.text for var in vars: newText = newText.replace('{{ ' + var.group(1) + ' }}', str(dict[var.group(1)])) - print(newText, end='', file=fd) + fd.write(newText) class template: @@ -91,10 +91,10 @@ class template: self.baseSectionSection = baseSection() context = [self.baseSectionSection] - forRE = re.compile('\s*\{% for (\S*) in (\S*) %\}') - endforRE = re.compile('\s*\{% endfor %\}') - ifRE = re.compile('\s*{% if (.*) %\}') - endifRE = re.compile('\s*\{% endif %\}') + forRE = re.compile(r'\s*\{% for (\S*) in (\S*) %\}') + endforRE = re.compile(r'\s*\{% endfor %\}') + ifRE = re.compile(r'\s*{% if (.*) %\}') + endifRE = re.compile(r'\s*\{% endif %\}') for line in lines: m = forRE.match(line) if m: