diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
similarity index 55%
rename from compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
rename to compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
index 0523b471..8dad9f9b 100755
--- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
@@ -25,21 +25,6 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         globals.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 non-replica array for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1])
-        self.local_check(a)
-
-        debug.info(2, "Testing 4x4 left replica array for dp cell")
-        a = factory.create(module_type="replica_bitcell_array",
-                           cols=4,
-                           rows=4,
-                           rbl=[1, 1],
-                           left_rbl=[0])
-        self.local_check(a)
-
         debug.info(2, "Testing 4x4 array left and right replica for dp cell")
         a = factory.create(module_type="replica_bitcell_array",
                            cols=4,
@@ -49,17 +34,6 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
                            right_rbl=[1])
         self.local_check(a)
 
-
-        # Sky 130 has restrictions on the symmetries
-        if OPTS.tech_name != "sky130":
-            debug.info(2, "Testing 4x4 array right only replica for dp cell")
-            a = factory.create(module_type="replica_bitcell_array",
-                               cols=4,
-                               rows=4,
-                               rbl=[1, 1],
-                               right_rbl=[1])
-            self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line
diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
new file mode 100755
index 00000000..3137802b
--- /dev/null
+++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class replica_bitcell_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 left replica array for dp cell")
+        a = factory.create(module_type="replica_bitcell_array",
+                           cols=4,
+                           rows=4,
+                           rbl=[1, 1],
+                           left_rbl=[0])
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
new file mode 100755
index 00000000..7f7ee74c
--- /dev/null
+++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class replica_bitcell_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 non-replica array for dp cell")
+        a = factory.create(module_type="replica_bitcell_array",
+                           cols=4,
+                           rows=4,
+                           rbl=[1, 1])
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())