From 224e35920859cfa8eaeddd92dc66f3617049a41f Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 18 Aug 2020 15:59:05 -0700 Subject: [PATCH] Fix pin order for replica array --- compiler/modules/local_bitcell_array.py | 5 ++--- compiler/tests/15_local_bitcell_array_1rw_1r_test.py | 9 +++++++-- compiler/tests/15_local_bitcell_array_test.py | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 413d1915..586ec51d 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -20,8 +20,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): """ def __init__(self, rows, cols, rbl, add_rbl=None, name=""): super().__init__(name, rows, cols, 0) - debug.info(2, "create local array of size {} rows x {} cols words".format(rows, - cols + sum(rbl))) + debug.info(2, "create local array of size {} rows x {} cols words".format(rows, cols)) self.rows = rows self.cols = cols @@ -103,7 +102,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): self.bitcell_array_inst = self.add_inst(name="array", mod=self.bitcell_array, offset=self.wl_inst.lr()) - self.connect_inst(self.bitline_names + self.array_wordline_inputs + ["vdd", "gnd"]) + self.connect_inst(self.array_wordline_inputs + self.bitline_names + ["vdd", "gnd"]) def place(self): """ Place the bitcelll array to the right of the wl driver. """ diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py index 9ef92bb2..c147341d 100755 --- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py @@ -22,12 +22,17 @@ class local_bitcell_array_1rw_1r_test(openram_test): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + globals.setup_bitcell() + debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[0, 0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[0, 0]) self.local_check(a) debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[0, 1]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py index 9200f5bf..a2f23d9c 100755 --- a/compiler/tests/15_local_bitcell_array_test.py +++ b/compiler/tests/15_local_bitcell_array_test.py @@ -29,7 +29,7 @@ class local_bitcell_array_test(openram_test): debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) self.local_check(a) - + globals.end_openram()