From 9ffba4b0529d3a50140810b75a0453b668a1cd0d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 13 Aug 2018 09:57:10 -0700 Subject: [PATCH 1/9] Add +x permissions on precharge and pbitcell tests --- compiler/tests/04_precharge_test.py | 0 compiler/tests/05_pbitcell_array_test.py | 0 2 files changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 compiler/tests/04_precharge_test.py mode change 100644 => 100755 compiler/tests/05_pbitcell_array_test.py diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py old mode 100644 new mode 100755 diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py old mode 100644 new mode 100755 From 49bee6a96eb459c64c30a571fb20a67d44338086 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 13 Aug 2018 14:09:49 -0700 Subject: [PATCH 2/9] Remove OEB signal since we split DIN/DOUT ports --- compiler/characterizer/delay.py | 6 ------ compiler/modules/control_logic.py | 21 ++++++++++----------- compiler/tests/21_ngspice_delay_test.py | 20 ++++++++++---------- technology/freepdk45/tech/tech.py | 2 +- technology/scn3me_subm/tech/tech.py | 2 +- 5 files changed, 22 insertions(+), 29 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2c639ee9..55a3bc06 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -166,7 +166,6 @@ class delay(): self.sf.write("\n* Generation of control signals\n") self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage) self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage) - self.stim.gen_constant(sig_name="OEb", v_val=self.vdd_voltage) self.sf.write("\n* Generation of global clock signal\n") self.stim.gen_constant(sig_name="CLK", v_val=0) @@ -621,7 +620,6 @@ class delay(): self.cycle_times.append(self.t_current) self.t_current += self.period self.web_values.append(1) - self.oeb_values.append(1) self.csb_values.append(1) self.add_data(data) @@ -637,7 +635,6 @@ class delay(): self.t_current += self.period self.web_values.append(1) - self.oeb_values.append(0) self.csb_values.append(0) self.add_data(data) @@ -654,7 +651,6 @@ class delay(): self.t_current += self.period self.web_values.append(0) - self.oeb_values.append(1) self.csb_values.append(0) self.add_data(data) @@ -674,7 +670,6 @@ class delay(): # Control logic signals each cycle self.web_values = [] - self.oeb_values = [] self.csb_values = [] # Address and data values for each address/data bit @@ -798,4 +793,3 @@ class delay(): """ Generates the control signals """ self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05) self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05) - self.stim.gen_pwl("oeb", self.cycle_times, self.oeb_values, self.period, self.slew, 0.05) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 99018a9a..d9f12589 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -52,7 +52,7 @@ class control_logic(design.design): dff = dff_inv() dff_height = dff.height - self.ctrl_dff_array = dff_inv_array(rows=3,columns=1) + self.ctrl_dff_array = dff_inv_array(rows=2,columns=1) self.add_mod(self.ctrl_dff_array) self.nand2 = pnand2(height=dff_height) @@ -93,10 +93,10 @@ class control_logic(design.design): #self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"]) # List of input control signals - self.input_list =["csb","web","oeb"] - self.dff_output_list =["cs_bar", "cs", "we_bar", "we", "oe_bar", "oe"] + self.input_list =["csb","web"] + self.dff_output_list =["cs_bar", "cs", "we_bar", "we"] # list of output control signals (for making a vertical bus) - self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs", "oe"] + self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Ooutputs to the bank @@ -190,14 +190,14 @@ class control_logic(design.design): (y_off,mirror)=self.get_offset(row) - # input: OE, clk_buf_bar,CS output: rbl_in_bar + # input: clk_buf_bar,CS output: rbl_in_bar self.rbl_in_bar_offset = vector(x_off, y_off) self.rbl_in_bar_inst=self.add_inst(name="nand3_rbl_in_bar", - mod=self.nand3, + mod=self.nand2, offset=self.rbl_in_bar_offset, mirror=mirror) - self.connect_inst(["clk_buf_bar", "oe", "cs", "rbl_in_bar", "vdd", "gnd"]) - x_off += self.nand3.width + self.connect_inst(["clk_buf_bar", "cs", "rbl_in_bar", "vdd", "gnd"]) + x_off += self.nand2.width # input: rbl_in_bar, output: rbl_in self.rbl_in_offset = vector(x_off, y_off) @@ -306,7 +306,7 @@ class control_logic(design.design): def route_dffs(self): """ Route the input inverters """ - dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we", "oe"]) + dff_out_map = zip(["dout_bar[{}]".format(i) for i in range(3)], ["cs", "we"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets) # Connect the clock rail to the other clock rail @@ -320,7 +320,6 @@ class control_logic(design.design): self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb") self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web") - self.copy_layout_pin(self.ctrl_dff_inst, "din[2]", "oeb") def add_dffs(self): @@ -388,7 +387,7 @@ class control_logic(design.design): def route_rbl_in(self): """ Connect the logic for the rbl_in generation """ - rbl_in_map = zip(["A", "B", "C"], ["clk_buf_bar", "oe", "cs"]) + rbl_in_map = zip(["A", "B"], ["clk_buf_bar", "cs"]) self.connect_vertical_bus(rbl_in_map, self.rbl_in_bar_inst, self.rail_offsets) # Connect the NAND3 output to the inverter diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 72bdbc65..33fb0e9c 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -61,16 +61,16 @@ class timing_sram_test(openram_test): 'write0_power': [0.04765188], 'write1_power': [0.04434999]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [11.69536], - 'delay_lh': [1.260921], - 'leakage_power': 0.00039469710000000004, - 'min_period': 20.0, - 'read0_power': [4.40238], - 'read1_power': [4.126633], - 'slew_hl': [1.259555], - 'slew_lh': [0.9150649], - 'write0_power': [4.988347], - 'write1_power': [4.473887]} + golden_data = {'delay_hl': [3.8551919999999997], + 'delay_lh': [2.649183], + 'leakage_power': 0.001692146, + 'min_period': 4.688, + 'read0_power': [17.34118], + 'read1_power': [16.63607], + 'slew_hl': [1.257066], + 'slew_lh': [1.211681], + 'write0_power': [21.73913], + 'write1_power': [18.39621]} else: self.assertTrue(False) # other techs fail diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 98e0fab3..f232a2a7 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -261,7 +261,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) #FIXME: We don't use these everywhere... spice["vdd_name"] = "vdd" spice["gnd_name"] = "gnd" -spice["control_signals"] = ["CSb", "WEb", "OEb"] +spice["control_signals"] = ["CSB", "WEB"] spice["data_name"] = "DATA" spice["addr_name"] = "ADDR" spice["minwidth_tx"] = drc["minwidth_tx"] diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 0bba8754..18ec5bca 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -224,7 +224,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) #FIXME: We don't use these everywhere... spice["vdd_name"] = "vdd" spice["gnd_name"] = "gnd" -spice["control_signals"] = ["CSb", "WEb", "OEb"] +spice["control_signals"] = ["CSB", "WEB"] spice["data_name"] = "DATA" spice["addr_name"] = "ADDR" spice["minwidth_tx"] = drc["minwidth_tx"] From f7f318d72e699a9b4e9d13927e261374263cf1c9 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 13 Aug 2018 14:47:03 -0700 Subject: [PATCH 3/9] Remove tri_en signals from bank control logic. --- compiler/modules/bank.py | 77 +++--------------- compiler/modules/bank_select.py | 8 +- compiler/modules/control_logic.py | 105 ------------------------- compiler/sram_base.py | 5 +- compiler/tests/21_hspice_delay_test.py | 20 ++--- 5 files changed, 25 insertions(+), 190 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 74730f8b..d4ab62e5 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -22,9 +22,9 @@ class bank(design.design): def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""): - mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", - "column_mux_array", "write_driver_array", "tri_gate_array", + "column_mux_array", "write_driver_array", "dff", "bank_select"] from importlib import reload for mod_name in mod_list: @@ -84,8 +84,7 @@ class bank(design.design): # the signals gated_*. if self.num_banks > 1: self.add_pin("bank_sel","INPUT") - for pin in ["s_en","w_en","tri_en_bar","tri_en", - "clk_buf_bar","clk_buf"]: + for pin in ["s_en","w_en","clk_buf_bar","clk_buf"]: self.add_pin(pin,"INPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -96,8 +95,6 @@ class bank(design.design): self.route_precharge_to_bitcell_array() self.route_col_mux_to_bitcell_array() self.route_sense_amp_to_col_mux_or_bitcell_array() - #self.route_sense_amp_to_trigate() - #self.route_tri_gate_out() self.route_sense_amp_out() self.route_wordline_driver() self.route_write_driver() @@ -121,8 +118,6 @@ class bank(design.design): self.add_column_mux_array() self.add_sense_amp_array() self.add_write_driver_array() - # Not needed for single bank - #self.add_tri_gate_array() # To the left of the bitcell array self.add_row_decoder() @@ -150,9 +145,9 @@ class bank(design.design): self.supply_rail_pitch = self.supply_rail_width + 4*self.m2_space # Number of control lines in the bus - self.num_control_lines = 6 + self.num_control_lines = 4 # The order of the control signals on the control bus: - self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"] + self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"] # These will be outputs of the gaters if this is multibank, if not, normal signals. if self.num_banks > 1: self.control_signals = ["gated_"+str for str in self.input_control_signals] @@ -176,7 +171,6 @@ class bank(design.design): def create_modules(self): """ Create all the modules using the class loader """ - self.tri = self.mod_tri_gate() self.bitcell = self.mod_bitcell() self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols, @@ -203,10 +197,6 @@ class bank(design.design): self.row_decoder = self.mod_decoder(rows=self.num_rows) self.add_mod(self.row_decoder) - self.tri_gate_array = self.mod_tri_gate_array(columns=self.num_cols, - word_size=self.word_size) - self.add_mod(self.tri_gate_array) - self.wordline_driver = self.mod_wordline_driver(rows=self.num_rows) self.add_mod(self.wordline_driver) @@ -316,22 +306,6 @@ class bank(design.design): temp.extend([self.prefix+"w_en", "vdd", "gnd"]) self.connect_inst(temp) - def add_tri_gate_array(self): - """ data tri gate to drive the data bus """ - y_offset = self.sense_amp_array.height+self.column_mux_height \ - + self.m2_gap + self.tri_gate_array.height - self.tri_gate_array_inst=self.add_inst(name="tri_gate_array", - mod=self.tri_gate_array, - offset=vector(0,y_offset).scale(-1,-1)) - - temp = [] - for i in range(self.word_size): - temp.append("sa_out[{0}]".format(i)) - for i in range(self.word_size): - temp.append("dout[{0}]".format(i)) - temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"]) - self.connect_inst(temp) - def add_row_decoder(self): """ Add the hierarchical row decoder """ @@ -447,7 +421,6 @@ class bank(design.design): self.precharge_array_inst, self.sense_amp_array_inst, self.write_driver_array_inst, -# self.tri_gate_array_inst, self.row_decoder_inst, self.wordline_driver_inst] # Add these if we use the part... @@ -493,10 +466,7 @@ class bank(design.design): control bus, power ring, etc. """ #The minimum point is either the bottom of the address flops, - #the column decoder (if there is one) or the tristate output - #driver. - # Leave room for the output below the tri gate. - #tri_gate_min_y_offset = self.tri_gate_array_inst.by() - 3*self.m2_pitch + #the column decoder (if there is one). write_driver_min_y_offset = self.write_driver_array_inst.by() - 3*self.m2_pitch row_decoder_min_y_offset = self.row_decoder_inst.by() if self.col_addr_size > 0: @@ -506,10 +476,10 @@ class bank(design.design): if self.num_banks>1: # The control gating logic is below the decoder - # Min of the control gating logic and tri gate. + # Min of the control gating logic and write driver. self.min_y_offset = min(col_decoder_min_y_offset - self.bank_select.height, write_driver_min_y_offset) else: - # Just the min of the decoder logic logic and tri gate. + # Just the min of the decoder logic logic and write driver. self.min_y_offset = min(col_decoder_min_y_offset, write_driver_min_y_offset) # The max point is always the top of the precharge bitlines @@ -603,20 +573,6 @@ class bank(design.design): self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset), vector(connect_br.x,yoffset), connect_br]) - def route_sense_amp_to_trigate(self): - """ Routing of sense amp output to tri_gate input """ - - for i in range(self.word_size): - # Connection of data_out of sense amp to data_in - tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).lc() - sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).bc() - - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=tri_gate_in) - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=sa_data_out) - self.add_path("metal3",[sa_data_out,tri_gate_in]) - def route_sense_amp_out(self): """ Add pins for the sense amp output """ for i in range(self.word_size): @@ -627,17 +583,6 @@ class bank(design.design): height=data_pin.height(), width=data_pin.width()), - def route_tri_gate_out(self): - """ Metal 3 routing of tri_gate output data """ - for i in range(self.word_size): - data_pin = self.tri_gate_array_inst.get_pin("out[{}]".format(i)) - self.add_layout_pin_rect_center(text="dout[{}]".format(i), - layer=data_pin.layer, - offset=data_pin.center(), - height=data_pin.height(), - width=data_pin.width()), - - def route_row_decoder(self): """ Routes the row decoder inputs and supplies """ @@ -782,8 +727,6 @@ class bank(design.design): # Connection from the central bus to the main control block crosses # pre-decoder and this connection is in metal3 connection = [] - #connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc())) - #connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc())) connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst.get_pin("en").lc())) connection.append((self.prefix+"w_en", self.write_driver_array_inst.get_pin("en").lc())) connection.append((self.prefix+"s_en", self.sense_amp_array_inst.get_pin("en").lc())) @@ -866,8 +809,6 @@ class bank(design.design): self.bitcell_array.output_load()) # output load of bitcell_array is set to be only small part of bl for sense amp. - data_t_DATA_delay = self.tri_gate_array.analytical_delay(bl_t_data_out_delay.slew, load) - - result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay + result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay return result diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 2abfb3c6..9a4b193e 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -19,9 +19,9 @@ class bank_select(design.design): design.design.__init__(self, name) # Number of control lines in the bus - self.num_control_lines = 6 + self.num_control_lines = 4 # The order of the control signals on the control bus: - self.input_control_signals = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"] + self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en"] # These will be outputs of the gaters if this is multibank self.control_signals = ["gated_"+str for str in self.input_control_signals] @@ -96,7 +96,7 @@ class bank_select(design.design): # These require OR (nor2+inv) gates since they are active low. # (writes occur on clk low) - if input_name in ("clk_buf", "tri_en_bar"): + if input_name in ("clk_buf"): self.logic_inst.append(self.add_inst(name=name_nor, mod=self.nor2, @@ -173,7 +173,7 @@ class bank_select(design.design): input_name = self.input_control_signals[i] gated_name = self.control_signals[i] - if input_name in ("clk_buf", "tri_en_bar"): + if input_name in ("clk_buf"): xoffset_bank_signal = xoffset_bank_sel_bar else: xoffset_bank_signal = xoffset_bank_sel diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index d9f12589..cf62851f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -101,8 +101,6 @@ class control_logic(design.design): self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Ooutputs to the bank self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"] - # # with tri/tri_en - # self.output_list = ["s_en", "w_en", "tri_en", "tri_en_bar", "clk_buf_bar", "clk_buf"] self.supply_list = ["vdd", "gnd"] @@ -237,71 +235,6 @@ class control_logic(design.design): self.row_end_inst.append(self.s_en_inst) - def add_trien_row(self, row): - x_off = self.ctrl_dff_array.width + self.internal_bus_width - (y_off,mirror)=self.get_offset(row) - - - x_off += self.nand2.width - - # BUFFER INVERTERS FOR TRI_EN - tri_en_offset = vector(x_off, y_off) - self.tri_en_inst=self.add_inst(name="inv_tri_en1", - mod=self.inv2, - offset=tri_en_offset, - mirror=mirror) - self.connect_inst(["pre_tri_en_bar", "pre_tri_en1", "vdd", "gnd"]) - x_off += self.inv2.width - - tri_en_buf1_offset = vector(x_off, y_off) - self.tri_en_buf1_inst=self.add_inst(name="tri_en_buf1", - mod=self.inv2, - offset=tri_en_buf1_offset, - mirror=mirror) - self.connect_inst(["pre_tri_en1", "pre_tri_en_bar1", "vdd", "gnd"]) - x_off += self.inv2.width - - tri_en_buf2_offset = vector(x_off, y_off) - self.tri_en_buf2_inst=self.add_inst(name="tri_en_buf2", - mod=self.inv8, - offset=tri_en_buf2_offset, - mirror=mirror) - self.connect_inst(["pre_tri_en_bar1", "tri_en", "vdd", "gnd"]) - - self.row_end_inst.append(self.tri_en_inst) - - def add_trien_bar_row(self, row): - x_off = self.ctrl_dff_array.width + self.internal_bus_width - (y_off,mirror)=self.get_offset(row) - - - # input: OE, clk_buf_bar output: tri_en_bar - tri_en_bar_offset = vector(x_off,y_off) - self.tri_en_bar_inst=self.add_inst(name="nand2_tri_en", - mod=self.nand2, - offset=tri_en_bar_offset, - mirror=mirror) - self.connect_inst(["clk_buf_bar", "oe", "pre_tri_en_bar", "vdd", "gnd"]) - x_off += self.nand2.width - - # BUFFER INVERTERS FOR TRI_EN - tri_en_bar_buf1_offset = vector(x_off, y_off) - self.tri_en_bar_buf1_inst=self.add_inst(name="tri_en_bar_buf1", - mod=self.inv2, - offset=tri_en_bar_buf1_offset, - mirror=mirror) - self.connect_inst(["pre_tri_en_bar", "pre_tri_en2", "vdd", "gnd"]) - x_off += self.inv2.width - - tri_en_bar_buf2_offset = vector(x_off, y_off) - self.tri_en_bar_buf2_inst=self.add_inst(name="tri_en_bar_buf2", - mod=self.inv8, - offset=tri_en_bar_buf2_offset, - mirror=mirror) - self.connect_inst(["pre_tri_en2", "tri_en_bar", "vdd", "gnd"]) - x_off += self.inv8.width - - self.row_end_inst.append(self.tri_en_bar_buf2_inst) def route_dffs(self): """ Route the input inverters """ @@ -474,44 +407,6 @@ class control_logic(design.design): self.connect_output(self.w_en_inst, "Z", "w_en") - def route_trien(self): - - # Connect the NAND2 output to the buffer - tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center() - inv_in_pos = self.tri_en_inst.get_pin("A").center() - mid1 = vector(tri_en_bar_pos.x,inv_in_pos.y) - self.add_wire(("metal1","via1","metal2"),[tri_en_bar_pos,mid1,inv_in_pos]) - - # Connect the INV output to the buffer - tri_en_pos = self.tri_en_inst.get_pin("Z").center() - inv_in_pos = self.tri_en_buf1_inst.get_pin("A").center() - mid_xoffset = 0.5*(tri_en_pos.x + inv_in_pos.x) - mid1 = vector(mid_xoffset,tri_en_pos.y) - mid2 = vector(mid_xoffset,inv_in_pos.y) - self.add_path("metal1",[tri_en_pos,mid1,mid2,inv_in_pos]) - - self.add_path("metal1",[self.tri_en_buf1_ist.get_pin("Z").center(), self.tri_en_buf2_inst.get_pin("A").center()]) - - self.connect_output(self.tri_en_buf2_inst, "Z", "tri_en") - - def route_trien_bar(self): - - trien_map = zip(["A", "B"], ["clk_buf_bar", "oe"]) - self.connect_vertical_bus(trien_map, self.tri_en_bar_inst, self.rail_offsets) - - # Connect the NAND2 output to the buffer - tri_en_bar_pos = self.tri_en_bar_inst.get_pin("Z").center() - inv_in_pos = self.tri_en_bar_buf1_inst.get_pin("A").center() - mid_xoffset = 0.5*(tri_en_bar_pos.x + inv_in_pos.x) - mid1 = vector(mid_xoffset,tri_en_bar_pos.y) - mid2 = vector(mid_xoffset,inv_in_pos.y) - self.add_path("metal1",[tri_en_bar_pos,mid1,mid2,inv_in_pos]) - - self.add_path("metal1",[self.tri_en_bar_buf1_inst.get_pin("Z").center(), self.tri_en_bar_buf2_inst.get_pin("A").center()]) - - self.connect_output(self.tri_en_bar_buf2_inst, "Z", "tri_en_bar") - - def route_sen(self): rbl_out_pos = self.rbl_inst.get_pin("out").bc() in_pos = self.pre_s_en_bar_inst.get_pin("A").lc() diff --git a/compiler/sram_base.py b/compiler/sram_base.py index c7044d61..812c0950 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -150,7 +150,7 @@ class sram_base(design): """ Add the horizontal and vertical busses """ # Vertical bus # The order of the control signals on the control bus: - self.control_bus_names = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"] + self.control_bus_names = ["clk_buf", "clk_buf_bar", "w_en", "s_en"] self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2", pitch=self.m2_pitch, offset=self.vertical_bus_offset, @@ -328,8 +328,7 @@ class sram_base(design): temp.append("A[{0}]".format(i)) if(self.num_banks > 1): temp.append("bank_sel[{0}]".format(bank_num)) - temp.extend(["s_en", "w_en", "tri_en_bar", "tri_en", - "clk_buf_bar","clk_buf" , "vdd", "gnd"]) + temp.extend(["s_en", "w_en", "clk_buf_bar","clk_buf" , "vdd", "gnd"]) self.connect_inst(temp) return bank_inst diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 0d256c5b..9b9eb2bd 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -62,16 +62,16 @@ class timing_sram_test(openram_test): 'write0_power': [0.0494321], 'write1_power': [0.0457268]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [6.0052], - 'delay_lh': [2.2886], - 'leakage_power': 0.025629199999999998, - 'min_period': 9.375, - 'read0_power': [8.8721], - 'read1_power': [8.3179], - 'slew_hl': [1.0746], - 'slew_lh': [0.413426], - 'write0_power': [8.6601], - 'write1_power': [8.0397]} + golden_data = {'delay_hl': [3.6602], + 'delay_lh': [2.2651], + 'leakage_power': 0.026040400000000002, + 'min_period': 4.688, + 'read0_power': [15.8985], + 'read1_power': [14.9719], + 'slew_hl': [1.1001], + 'slew_lh': [0.4111598], + 'write0_power': [19.4539], + 'write1_power': [16.8561]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results From 5ff49d322d282ff51201729e3b910dcec10a7431 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 13 Aug 2018 15:14:52 -0700 Subject: [PATCH 4/9] bank_sel_bar only used for clk now --- compiler/modules/bank_select.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 9a4b193e..f89f16be 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -161,7 +161,7 @@ class bank_select(design.design): self.add_label_pin(text="bank_sel_bar", layer="metal2", offset=vector(xoffset_bank_sel_bar, 0), - height=2*self.inv.height) + height=self.inv.height) self.add_via_center(layers=("metal1","via1","metal2"), offset=bank_sel_bar_pin.rc()) From 3420b1002c37ba79d7a878256fd0d79b5f7a8cbe Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 14 Aug 2018 10:09:41 -0700 Subject: [PATCH 5/9] Connect data and column DFF clocks in 1 bank. --- compiler/modules/bank.py | 62 ++++------------------------ compiler/modules/control_logic.py | 9 ++-- compiler/modules/dff_array.py | 37 +++++++---------- compiler/modules/replica_bitline.py | 6 +-- compiler/sram_1bank.py | 44 +++++++++++++++----- compiler/sram_base.py | 6 +-- compiler/tests/20_sram_1bank_test.py | 2 +- 7 files changed, 69 insertions(+), 97 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index d4ab62e5..ea7881ed 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -101,7 +101,6 @@ class bank(design.design): self.route_row_decoder() self.route_column_address_lines() self.route_control_lines() - self.add_control_pins() if self.num_banks > 1: self.route_bank_select() @@ -505,13 +504,15 @@ class bank(design.design): # and control lines. # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs - control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, 0) - control_bus_length = self.bitcell_array_inst.uy() - self.bus_xoffset = self.create_vertical_bus(layer="metal2", - pitch=self.m2_pitch, - offset=control_bus_offset, - names=self.control_signals, - length=control_bus_length) + control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset) + control_bus_length = self.max_y_offset - self.min_y_offset + self.bus_xoffset = self.create_bus(layer="metal2", + pitch=self.m2_pitch, + offset=control_bus_offset, + names=self.control_signals, + length=control_bus_length, + vertical=True, + make_pins=(self.num_banks==1)) @@ -750,52 +751,7 @@ class bank(design.design): offset=control_via_pos, rotate=90) - def add_control_pins(self): - """ Add the control signal input pins """ - for ctrl in self.control_signals: - # xoffsets are the center of the rail - x_offset = self.bus_xoffset[ctrl].x - 0.5*self.m2_width - if self.num_banks > 1: - # it's not an input pin if we have multiple banks - self.add_label_pin(text=ctrl, - layer="metal2", - offset=vector(x_offset, self.min_y_offset), - width=self.m2_width, - height=self.max_y_offset-self.min_y_offset) - else: - self.add_layout_pin(text=ctrl, - layer="metal2", - offset=vector(x_offset, self.min_y_offset), - width=self.m2_width, - height=self.max_y_offset-self.min_y_offset) - - - def connect_rail_from_right(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pin = inst.get_pin(pin).lc() - rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) - self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) - # Bring it up to M2 for M2/M3 routing - self.add_via(layers=("metal1","via1","metal2"), - offset=in_pin + contact.m1m2.offset, - rotate=90) - self.add_via(layers=("metal2","via2","metal3"), - offset=in_pin + self.m2m3_via_offset, - rotate=90) - - - def connect_rail_from_left(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pin = inst.get_pin(pin).rc() - rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y) - self.add_wire(("metal3","via2","metal2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)]) - self.add_via(layers=("metal1","via1","metal2"), - offset=in_pin + contact.m1m2.offset, - rotate=90) - self.add_via(layers=("metal2","via2","metal3"), - offset=in_pin + self.m2m3_via_offset, - rotate=90) def analytical_delay(self, slew, load): """ return analytical delay of the bank""" diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index cf62851f..5e744bfa 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -99,7 +99,7 @@ class control_logic(design.design): self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch - # Ooutputs to the bank + # Outputs to the bank self.output_list = ["s_en", "w_en", "clk_buf_bar", "clk_buf"] self.supply_list = ["vdd", "gnd"] @@ -137,10 +137,11 @@ class control_logic(design.design): # This offset is used for placement of the control logic in # the SRAM level. self.control_logic_center = vector(self.ctrl_dff_inst.rx(), self.rbl_inst.by()) - - self.height = self.rbl_inst.uy() + + # Extra pitch on top and right + self.height = self.rbl_inst.uy() + self.m3_pitch # Max of modules or logic rows - self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch def add_routing(self): diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 5a09ae33..ef59f8a6 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -125,28 +125,21 @@ class dff_array(design.design): # Create vertical spines to a single horizontal rail clk_pin = self.dff_insts[0,0].get_pin("clk") debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2") - if self.columns==1: - self.add_layout_pin(text="clk", - layer="metal2", - offset=clk_pin.ll().scale(1,0), - width=self.m2_width, - height=self.height) - else: - self.add_layout_pin_segment_center(text="clk", - layer="metal3", - start=vector(0,self.m3_pitch+self.m3_width), - end=vector(self.width,self.m3_pitch+self.m3_width)) - for col in range(self.columns): - clk_pin = self.dff_insts[0,col].get_pin("clk") - # Make a vertical strip for each column - self.add_rect(layer="metal2", - offset=clk_pin.ll().scale(1,0), - width=self.m2_width, - height=self.height) - # Drop a via to the M3 pin - self.add_via_center(layers=("metal2","via2","metal3"), - offset=vector(clk_pin.cx(),self.m3_pitch+self.m3_width)) - + self.add_layout_pin_segment_center(text="clk", + layer="metal3", + start=vector(0,self.m3_pitch+self.m3_width), + end=vector(self.width,self.m3_pitch+self.m3_width)) + for col in range(self.columns): + clk_pin = self.dff_insts[0,col].get_pin("clk") + # Make a vertical strip for each column + self.add_rect(layer="metal2", + offset=clk_pin.ll().scale(1,0), + width=self.m2_width, + height=self.height) + # Drop a via to the M3 pin + self.add_via_center(layers=("metal2","via2","metal3"), + offset=vector(clk_pin.cx(),self.m3_pitch+self.m3_width)) + def analytical_delay(self, slew, load=0.0): diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index bf6b8f92..941304e8 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -42,9 +42,9 @@ class replica_bitline(design.design): #self.add_lvs_correspondence_points() - # Plus a pitch for the WL contacts on the RBL - self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m1_pitch - self.height = max(self.rbl_inst.uy(), self.dc_inst.uy()) + # Extra pitch on top and right + self.width = self.rbl_inst.rx() - self.dc_inst.lx() + self.m2_pitch + self.height = max(self.rbl_inst.uy(), self.dc_inst.uy()) + self.m3_pitch self.DRC_LVS() diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 7d99299d..d58bcc85 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -29,26 +29,29 @@ class sram_1bank(sram_base): # No orientation or offset self.bank_inst = self.add_bank(0, [0, 0], 1, 1) + # The control logic is placed such that the center (between the delay/RBL and + # the actual control logic is aligned with the center of the bank (between + # the sense amps/column mux and cell array) control_pos = vector(-self.control_logic.width - self.m3_pitch, self.bank.bank_center.y - self.control_logic.control_logic_center.y) self.add_control_logic(position=control_pos) - # Leave room for the control routes to the left of the flops + # The row address bits are placed above the control logic aligned on the right. row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width, - control_pos.y + self.control_logic.height + self.m1_pitch) + self.control_logic_inst.uy()) self.add_row_addr_dff(row_addr_pos) # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk data_gap = -self.m2_pitch*(self.word_size+1) # Add the column address below the bank under the control - # Keep it aligned with the data flops + # The column address flops are aligned with the data flops if self.col_addr_dff: col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width, data_gap - self.col_addr_dff.height) self.add_col_addr_dff(col_addr_pos) - # Add the data flops below the bank + # Add the data flops below the bank to the right of the center of bank: # This relies on the center point of the bank: # decoder in upper left, bank in upper right, sensing in lower right. # These flops go below the sensing and leave a gap to channel route to the @@ -104,13 +107,34 @@ class sram_1bank(sram_base): def route_clk(self): """ Route the clock network """ - debug.warning("Clock is top-level must connect.") - # For now, just have four clock pins for the address (x2), data, and control - if self.col_addr_dff: - self.copy_layout_pin(self.col_addr_dff_inst, "clk") - self.copy_layout_pin(self.row_addr_dff_inst, "clk") - self.copy_layout_pin(self.data_dff_inst, "clk") + + # This is the actual input to the SRAM self.copy_layout_pin(self.control_logic_inst, "clk") + + debug.warning("Clock is top-level must connect.") + + # Connect all of these clock pins to the clock in the central bus + # This is something like a "spine" clock distribution. The two spines + # are clk_buf and clk_buf_bar + bank_clk_buf_pin = self.bank_inst.get_pin("clk_buf") + bank_clk_buf_pos = bank_clk_buf_pin.center() + bank_clk_buf_bar_pin = self.bank_inst.get_pin("clk_buf_bar") + bank_clk_buf_bar_pos = bank_clk_buf_bar_pin.center() + + if self.col_addr_dff: + dff_clk_pin = self.col_addr_dff_inst.get_pin("clk") + dff_clk_pos = dff_clk_pin.center() + mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y) + self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos]) + + self.copy_layout_pin(self.row_addr_dff_inst, "clk") + #self.copy_layout_pin(self.data_dff_inst, "clk") + + data_dff_clk_pin = self.data_dff_inst.get_pin("clk") + data_dff_clk_pos = data_dff_clk_pin.center() + mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y) + self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos]) + def route_vdd_gnd(self): """ Propagate all vdd/gnd pins up to this level for all modules """ diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 812c0950..c10019ff 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -362,8 +362,7 @@ class sram_base(design): inputs.append("ADDR[{}]".format(i)) outputs.append("A[{}]".format(i)) - # FIXME clk->clk_buf - self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) def add_data_dff(self, position): """ Add and place all data flops """ @@ -377,8 +376,7 @@ class sram_base(design): inputs.append("DIN[{}]".format(i)) outputs.append("BANK_DIN[{}]".format(i)) - # FIXME clk->clk_buf_bar - self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) def add_control_logic(self, position): """ Add and place control logic """ diff --git a/compiler/tests/20_sram_1bank_test.py b/compiler/tests/20_sram_1bank_test.py index 4b929e87..8b83f54a 100755 --- a/compiler/tests/20_sram_1bank_test.py +++ b/compiler/tests/20_sram_1bank_test.py @@ -35,7 +35,7 @@ class sram_1bank_test(openram_test): debug.info(1, "Single bank, eight way column mux with control logic") a = sram(word_size=2, num_words=128, num_banks=1, name="sram4") self.local_check(a, final_verification=True) - + globals.end_openram() # instantiate a copy of the class to actually run the test From 8900edbe121eedfd1c8b809f664747f22db40805 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 14 Aug 2018 10:36:35 -0700 Subject: [PATCH 6/9] Finalize single bank clock routing. --- compiler/sram_1bank.py | 28 ++++++++++++++++++++-------- compiler/sram_base.py | 3 +-- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index d58bcc85..4d2d72eb 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -29,10 +29,12 @@ class sram_1bank(sram_base): # No orientation or offset self.bank_inst = self.add_bank(0, [0, 0], 1, 1) - # The control logic is placed such that the center (between the delay/RBL and - # the actual control logic is aligned with the center of the bank (between + # The control logic is placed such that the vertical center (between the delay/RBL and + # the actual control logic is aligned with the vertical center of the bank (between # the sense amps/column mux and cell array) - control_pos = vector(-self.control_logic.width - self.m3_pitch, + # The x-coordinate is placed to allow a single clock wire (plus an extra pitch) + # up to the row address DFFs. + control_pos = vector(-self.control_logic.width - 2*self.m2_pitch, self.bank.bank_center.y - self.control_logic.control_logic_center.y) self.add_control_logic(position=control_pos) @@ -111,11 +113,10 @@ class sram_1bank(sram_base): # This is the actual input to the SRAM self.copy_layout_pin(self.control_logic_inst, "clk") - debug.warning("Clock is top-level must connect.") - # Connect all of these clock pins to the clock in the central bus # This is something like a "spine" clock distribution. The two spines # are clk_buf and clk_buf_bar + bank_clk_buf_pin = self.bank_inst.get_pin("clk_buf") bank_clk_buf_pos = bank_clk_buf_pin.center() bank_clk_buf_bar_pin = self.bank_inst.get_pin("clk_buf_bar") @@ -126,14 +127,25 @@ class sram_1bank(sram_base): dff_clk_pos = dff_clk_pin.center() mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y) self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos]) - - self.copy_layout_pin(self.row_addr_dff_inst, "clk") - #self.copy_layout_pin(self.data_dff_inst, "clk") data_dff_clk_pin = self.data_dff_inst.get_pin("clk") data_dff_clk_pos = data_dff_clk_pin.center() mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y) self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos]) + + # This uses a metal2 track to the right of the control/row addr DFF + # to route vertically. + control_clk_buf_pin = self.control_logic_inst.get_pin("clk_buf") + control_clk_buf_pos = control_clk_buf_pin.rc() + row_addr_clk_pin = self.row_addr_dff_inst.get_pin("clk") + row_addr_clk_pos = row_addr_clk_pin.rc() + mid1_pos = vector(self.row_addr_dff_inst.rx() + self.m2_pitch, + row_addr_clk_pos.y) + mid2_pos = vector(mid1_pos.x, + control_clk_buf_pos.y) + # Note, the via to the control logic is taken care of when we route + # the control logic to the bank + self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, mid2_pos, control_clk_buf_pos]) def route_vdd_gnd(self): diff --git a/compiler/sram_base.py b/compiler/sram_base.py index c10019ff..a11b0984 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -346,8 +346,7 @@ class sram_base(design): inputs.append("ADDR[{}]".format(i+self.col_addr_size)) outputs.append("A[{}]".format(i+self.col_addr_size)) - # FIXME clk->clk_buf - self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) def add_col_addr_dff(self, position): From 36bfd2932a484fc21a47f173c1df53316e48f37a Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 14 Aug 2018 10:51:02 -0700 Subject: [PATCH 7/9] Update delay results with new clock routing --- compiler/tests/21_hspice_delay_test.py | 36 +++++++++++------------ compiler/tests/21_ngspice_delay_test.py | 38 ++++++++++++------------- 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 9b9eb2bd..dd2d14de 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,27 +51,27 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5614], - 'delay_lh': [0.22929839999999999], - 'leakage_power': 0.0020326, + golden_data = {'delay_hl': [2.5829000000000004], + 'delay_lh': [0.2255964], + 'leakage_power': 0.0019498999999999996, 'min_period': 4.844, - 'read0_power': [0.0497676], - 'read1_power': [0.0463576], - 'slew_hl': [0.1119293], - 'slew_lh': [0.0237043], - 'write0_power': [0.0494321], - 'write1_power': [0.0457268]} + 'read0_power': [0.055371399999999994], + 'read1_power': [0.0520225], + 'slew_hl': [0.0794261], + 'slew_lh': [0.0236264], + 'write0_power': [0.06545659999999999], + 'write1_power': [0.057846299999999996]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [3.6602], - 'delay_lh': [2.2651], - 'leakage_power': 0.026040400000000002, + golden_data = {'delay_hl': [4.0249], + 'delay_lh': [2.2611], + 'leakage_power': 0.0257389, 'min_period': 4.688, - 'read0_power': [15.8985], - 'read1_power': [14.9719], - 'slew_hl': [1.1001], - 'slew_lh': [0.4111598], - 'write0_power': [19.4539], - 'write1_power': [16.8561]} + 'read0_power': [24.9279], + 'read1_power': [24.0219], + 'slew_hl': [0.8500753999999999], + 'slew_lh': [0.4122653], + 'write0_power': [28.197600000000005], + 'write1_power': [25.685]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 33fb0e9c..cd41c798 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.562671], - 'delay_lh': [0.2320771], - 'leakage_power': 0.00102373, + golden_data = {'delay_hl': [2.584251], + 'delay_lh': [0.22870469999999998], + 'leakage_power': 0.0009567935, 'min_period': 4.844, - 'read0_power': [0.047404110000000006], - 'read1_power': [0.0438884], - 'slew_hl': [0.1140206], - 'slew_lh': [0.02492785], - 'write0_power': [0.04765188], - 'write1_power': [0.04434999]} + 'read0_power': [0.0547588], + 'read1_power': [0.051159970000000006], + 'slew_hl': [0.08164099999999999], + 'slew_lh': [0.025474979999999998], + 'write0_power': [0.06513271999999999], + 'write1_power': [0.058057000000000004]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [3.8551919999999997], - 'delay_lh': [2.649183], - 'leakage_power': 0.001692146, - 'min_period': 4.688, - 'read0_power': [17.34118], - 'read1_power': [16.63607], - 'slew_hl': [1.257066], - 'slew_lh': [1.211681], - 'write0_power': [21.73913], - 'write1_power': [18.39621]} + golden_data = {'delay_hl': [4.221382999999999], + 'delay_lh': [2.6459520000000003], + 'leakage_power': 0.0013865260000000001, + 'min_period': 4.688, + 'read0_power': [26.699669999999998], + 'read1_power': [26.13123], + 'slew_hl': [0.9821776000000001], + 'slew_lh': [1.5791520000000001], + 'write0_power': [30.71939], + 'write1_power': [27.44753]} else: self.assertTrue(False) # other techs fail From 6e332e581a19f8db37ce32cab373d4700e0ed228 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 15 Aug 2018 09:46:23 -0700 Subject: [PATCH 8/9] Updated to include local magic rules --- compiler/verify/magic.py | 1 + technology/scn3me_subm/tech/LICENSE.txt | 10 + .../scn3me_subm/tech/SCN3ME_SUBM.30.tech | 7881 +++++++++++++++++ 3 files changed, 7892 insertions(+) create mode 100644 technology/scn3me_subm/tech/LICENSE.txt create mode 100644 technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 5ae0ccd7..112b1257 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -78,6 +78,7 @@ def write_magic_script(cell_name, gds_name, extract=False): f = open(run_file, "w") f.write("#!/bin/sh\n") f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) + f.write("path sys +{}/tech\n".format(OPTS.openram_tech)) f.write("tech load SCN3ME_SUBM.30\n") #gf.write("scalegrid 1 8\n") #f.write("gds rescale no\n") diff --git a/technology/scn3me_subm/tech/LICENSE.txt b/technology/scn3me_subm/tech/LICENSE.txt new file mode 100644 index 00000000..0d923fcb --- /dev/null +++ b/technology/scn3me_subm/tech/LICENSE.txt @@ -0,0 +1,10 @@ +The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following +license information: +--------------------------------------------------------------- +Tim Edwards +Open Circuit Design +v1.0 April 2013 +v1.1 May 2015 +v1.2 April 2017 +--------------------------------------------------------------- +GPL Copyright (c) 2017 diff --git a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech new file mode 100644 index 00000000..bf6ce64b --- /dev/null +++ b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech @@ -0,0 +1,7881 @@ +tech + format 32 + scmos +end + +version + version 2002a + description "SCMOS: Submit as technology.lambda: SCN3ME_SUBM.30 [to process: AMIc5]" +end + +planes + well,w + implant,i + select,s + cap,c + active,a + metal1,m1 + metal2,m2 + metal3,m3 + oxide,ox + comment + xp + contact + via1,v1 + via2,v2 + fill +end + +types + well nwell,nw + well pwell,pw + implant n_field_implant,nfi + implant p_field_implant,pfi + select nselect,ns + select pselect,ps + cap electrode,poly2,el,p2 + cap electrodecontact,poly2contact,poly2c,p2c,elc + cap p2m12contact,p2m12c + cap electrodecap,ecap,poly2cap,p2cap,pcap + contact genericpoly2contact,gc2 + active ntransistor,nfet + active ptransistor,pfet + active diffusion,diff + active transistor,fet + active ndiffusion,ndif,green + active pdiffusion,pdif,brown + active ndcontact,ndc + active pdcontact,pdc + active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd + active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd + active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc + active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc + active polysilicon,red,poly,p + active polycontact,pcontact,polycut,pc + contact genericcontact,gcontact,gc + metal1 metal1,m1,blue + metal1 pseudo_rmetal1,prm1 + metal1 rmetal1,rm1 + metal1 fillm1,fm1 + metal1 m2contact,m2cut,m2c,via1,v1 + metal2 metal2,m2,purple + metal2 pseudo_rmetal2,prm2 + metal2 rmetal2,rm2 + metal2 fillm2,fm2 + via1 gv1 + metal2 m3contact,m3cut,m3c,via2,v2 + metal3 metal3,m3,cyan + metal3 pseudo_rmetal3,prm3 + metal3 rmetal3,rm3 + metal3 fillm3,fm3 + via2 gv2 + metal3 pad + oxide glass + cap high_resist,hr + cap poly2_high_resist,phr + active pseudo_rpoly,prp + active rpoly,rp + cap pseudo_rpoly2,prp2 + cap rpoly2,rp2 + active pseudo_rndiffusion,prnd + active rndiffusion,rndiff,rnd + active pseudo_rpdiffusion,prpd + active rpdiffusion,rpdiff,rpd + active pseudo_rnwell,prnwell,prnw + active rnwell,rnw + implant filln,fn + fill filla,fa + fill fillb,fb + active fillp,fp + active fillapm,fapm + xp xp + xp m1p + xp m2p + xp m3p + comment comment + comment bb +end + +contact + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + psc psd metal1 + m2c metal1 metal2 + m3c metal2 metal3 + stackable pc m2c pm12contact,pm12c + stackable pdc m2c pdm12contact,pdm12c + stackable psc m2c psm12contact,psm12c,pom12c,pwm12c + stackable ndc m2c ndm12contact,ndm12c + stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c + stackable m2c m3c m123contact,m123c +end + +styles + styletype mos + nwell 12 + pwell 13 + nfi 53 + pfi 54 + nselect 43 + pselect 44 + diff 25 + tran 2 4 + ndiff 2 + pdiff 4 + nsd 3 + psd 5 + nfet 6 7 + pfet 8 9 + ndc 2 20 32 + pdc 4 20 32 + nsc 3 20 32 + psc 5 20 32 + poly 1 + pcontact 1 20 32 + gc 32 + metal1 20 + rm1 20 48 + prm1 48 + m1p 20 34 + fm1 20 34 + fp 1 34 + fa 32 + fb 45 34 + fn 45 34 + fapm 1 20 21 34 + gv1 55 + m2contact 20 21 55 + p2m12contact 14 20 21 32 55 + metal2 21 + rm2 21 48 + prm2 48 + m2p 21 34 + fm2 21 34 + gv2 56 + m3contact 21 22 56 + metal3 22 + rm3 22 48 + prm3 48 + m3p 22 34 + fm3 22 34 + pad 22 23 34 38 + glass 34 + xp 25 34 + ecap 10 14 + poly2 14 + p2c 14 20 32 + gc2 19 + hr 10 + phr 14 48 + rp 47 48 + prp 48 + rp2 14 48 + prp2 48 + rnd 2 48 + prnd 48 + rpd 4 53 + prpd 53 + rnw 12 53 + prnw 54 + comment 45 + bb 32 + error_p 42 + error_s 42 + error_ps 42 + magnet 54 + rotate 57 + fence 59 +end + +compose + compose nfet poly ndiff + compose pfet poly pdiff + paint diff nselect ndiff + paint diff pselect pdiff + compose tran poly diff + paint tran nselect nfet + paint tran pselect pfet + paint psd ns ndiff + paint nsd ps pdiff + paint ndiff ps psd + paint pdiff ns nsd + paint pad m1 pad + paint pad m2 pad + paint pad m2c pad + paint pfi nwell nfi + paint nfi pwell pfi + paint ndc nwell pdc + paint nfet nwell pfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint pdc pwell ndc + paint pfet pwell nfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint poly2 poly ecap + erase ecap poly poly2 + paint p2c poly2 p2c + paint p2c ecap p2c + paint p2m12c poly2 p2m12c + paint p2m12c ecap p2m12c + paint pad m3 pad + compose phr poly2 hr + paint hr poly2 phr + paint poly2 hr phr + erase phr hr poly2 +#CRE/CRM + compose rm1 prm1 m1 + compose rm2 prm2 m2 + compose rm3 prm3 m3 + compose rp prp poly + compose rp2 prp2 poly2 + compose rnd prnd ndiff + compose rpd prpd pdiff + paint nwell rnw space + paint nwell prnw space + paint poly fp fp + paint m1 fm1 fm1 + paint m2 fm2 fm2 + paint m3 fm3 fm3 +end + +connect + nwell,nsc/a,nsd nwell,nsc/a,nsd + pwell,psc/a,psd pwell,psc/a,psd + m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 + m3,fm3,fapm,m3c/m3 m3,fm3,fapm,m3c/m3 + ndiff,ndc/a,pdiff,pdc/a ndiff,ndc/a,pdiff,pdc/a + poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a + gc2 poly2,ecap,metal1 + p2c poly2,ecap,m1,fm1,fapm,m2c/m1 + p2m12c poly2,ecap,m1,fm1,fapm,m2c/m1,m2,fm2,fapm,m2c/m2,m3c/m2 + poly2,ecap,p2c,p2m12c poly2,ecap,p2c,p2m12c + gc2 poly2,ecap,m1,fm1,fapm,m2c/m1 + gc poly,fp,ndiff,pdiff,nsd,psd,m1,fm1,fapm,m2c/m1 + gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 + gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm + pad m1,fm1,m2,fm2,m3,fm3 + rm1 prm1 + rm2 prm2 + rm3 prm3 + rnw prnw + rp prp + rp2 prp2 + rnd prnd + rpd prpd + phr hr +end + +cifoutput + +style lambda=0.30(p) + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + layer CWP pwell + bloat-or ndiff,rnd,ndc/a,nfet * 180 + bloat-or psd,psc/a * 90 + bloat-or pfi * 120 + grow 90 + shrink 90 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA ndc/m1,nsc/m1 + squares 30 60 90 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 30 60 90 + calma 48 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 30 60 90 + calma 47 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCE p2c,p2m12c + squares 30 60 90 + calma 55 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +style fill-only + scalefactor 30 15 + + layer 100 fp + calma 100 0 + + layer 101 fm1 + calma 101 0 + + layer 102 fm2 + calma 102 0 + + layer 103 fm3 + calma 103 0 + + layer 109 fa + or fb + calma 109 0 + + layer 119 fn + calma 119 0 + +style fapm-boxes + +# this output style creates fill boxes automatically (to meet minimum +# density requirements for poly and metal layers) 5 microns outside of +# drawn layout IF: 1. you have a flattened version of your chip +# 2. over which you paint the special fill layer 'fa', preferably with +# a size that is a multiple of 7 + n * (7 + 4), 3. set 'cif +# ostype fapm-boxes' and cif out to a file (this actually creates the +# fill boxes on cif/strm layer '110' using the magic 'squares' +# command), 4. cif in the resulting file (which creates boxes on magic +# layer 'fapm') and place this cell onto your chip (and verify absence +# of drc errors or shorts), then 5. cif out under your regular cif out +# style, where the 'fapm' layer creates fill boxes on poly and all +# metal layers. + + scalefactor 30 15 + + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + or fm3,m3,rm3,m3c/m3 + or glass,pad + grow 510 + and fa + + layer 110 fa + squares 0 210 120 + and-not CRIT + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + +style fapm-stripes + scalefactor 30 15 + +# this output style creates the above layer 110 as stripes for reduced size +# HOWEVER it requires each 'fa' box to first be an exact multiple as above +# and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box +# to be a 1-lambda wide layer 'fb' box -- else you won't get strips! + + templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c + or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + or fm3,m3,rm3,m3c/m3 + or glass,pad + grow 510 + and fa + + templayer FB fa + or fb + squares 0 210 120 + and-not CRIT + + layer 110 fa + squares 0 210 120 + and-not CRIT + or FB + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + + +style lambda=0.30(cp) + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + layer CWP pwell + bloat-or ndiff,rnd,ndc/a,nfet * 180 + bloat-or psd,psc/a * 90 + bloat-or pfi * 120 + grow 90 + shrink 90 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC ndc/m1,nsc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 30 60 90 + calma 25 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC p2c,p2m12c + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.30(c) + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC ndc/m1,nsc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 30 60 90 + calma 25 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC p2c,p2m12c + squares 30 60 90 + calma 25 0 + + layer CCC gc2 + squares 0 60 90 + calma 25 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.30() + scalefactor 30 15 + + layer CWN nwell,rnw + bloat-or pdiff,rpd,pdc/a,pfet * 180 + bloat-or nsd,nsc/a * 90 + bloat-or nfi * 120 + grow 90 + shrink 90 + labels nwell,rnw + calma 42 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*60) Or ps +#XDN = (ndiff*60) Or ns +#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 15 + grow 15 + grow 15 + shrink 15 + +#final nselect + templayer FSN + bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 15 + grow 15 + grow 15 + shrink 15 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA ndc/m1,nsc/m1 + squares 30 60 90 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 30 60 90 + calma 48 0 + + layer CPG poly,rp,nfet,pfet,fet,pc/a + labels poly,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 30 60 90 + calma 47 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCE p2c,p2m12c + squares 30 60 90 + calma 55 0 + + layer CCE gc2 + squares 0 60 90 + calma 55 0 + + layer CCC gc + squares 0 60 90 + calma 25 0 + + layer CV1 m2c/m1,p2m12c + squares 30 60 90 + calma 50 0 + + layer CV1 gv1 + squares 0 60 90 + calma 50 0 + + layer CV2 m3c/m2 + squares 30 60 90 + calma 61 0 + + layer CV2 gv2 + squares 0 60 90 + calma 61 0 + + + templayer XPAD1 pad + shrink 180 + + templayer XPAD2 XPAD1 + shrink 180 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 240 60 300 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 60 60 300 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 109 fa + or fb + squares 0 210 120 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 210 120 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 210 120 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 210 120 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 210 120 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3 + labels m3,rm3,m3c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer COG pad + shrink 600 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CHR hr,phr + labels hr,phr + calma 34 0 + + layer CEL poly2,ecap,phr,p2c,p2m12c + labels poly2,ecap,phr,p2c,p2m12c + calma 56 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp + labels rp,prp + calma 67 0 + layer CRD rnd,rpd,prnd,prpd + labels rnd,rpd,prnd,prpd + calma 66 0 + layer CRE rnw,rp,rnd,rpd,rp2 + labels rnw,rp,rnd,rpd,rp2 + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRG2 rp2,prp2 + labels rp2,prp2 + calma 68 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +end + +cifinput + +style lambda=0.30(p) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(s) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(ps) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30() + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CV1 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CV1 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CV1 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer ndc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and CV1 + and CV2 + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and CV1 + and CV2 + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 30 + grow 15 + shrink 15 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and-not CV1 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer pc CCP + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCP 47 * + + layer pc CCC + and CV1 + and CV2 + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and-not CV1 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer p2c CCE + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCE 55 * + + layer p2c CCC + and CV1 + and CV2 + and CPG + and CEL + and-not CPC + and-not CAA + grow 30 + and CM1 + grow 15 + shrink 15 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc2 CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc2 CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer m2c CV1 + and-not CV2 + and-not CCC + and-not CCE + and-not CCP + and-not CCA + and-not XP + grow 30 + and CM2 + and CM1 + grow 15 + shrink 15 + calma CV1 50 * + + + + layer p2m12c CV1 + and-not CV2 + and CCE + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer p2m12c CV1 + and-not CV2 + and CCC + grow 30 + and CM2 + and CM1 + and CPG + and CEL + grow 15 + shrink 15 + calma CV1 50 * + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + + and-not CV1 + and-not XP + grow 30 + and CM3 + and CM2 + grow 15 + shrink 15 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(c) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cs) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cps) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + + +style lambda=0.30(cp) + scalefactor 30 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc2 CCA + and CEL + calma CCA 48 * + + layer gc2 CCP + and CEL + calma CCP 47 * + + layer gc2 CCC + and CEL + calma CCC 25 * + + layer gc2 CCE + and CEL + calma CCE 55 * + + layer gc2 CCA + and CPC + and-not CPG + calma CCA 48 * + + layer gc2 CCP + and CPC + and-not CPG + calma CCP 47 * + + layer gc2 CCC + and CPC + and-not CPG + calma CCC 25 * + + layer gc2 CCE + and CPC + and-not CPG + calma CCE 55 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer hr CHR + labels CHR + calma CHR 34 * + + layer phr CEL + and CHR + calma CEL 56 * + + layer ecap CEL + and CPG + labels CEL + calma CEL 56 * + + layer poly2 CEL + and-not CPG + labels CEL + calma CEL 56 * + + layer rp2 CEL + and CRG2 + calma CEL 56 * + + layer pseudo_rpoly2 CRG2 + and-not CRE + calma CRG2 68 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRM 70 * + +style fill-only + scalefactor 30 +# scalefactor 100 + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fa 109 + or fb + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + +end + +mzrouter + style irouter +# layer hCost vCost jogCost hintCost + layer metal3 1 2 2 1 + layer metal2 2 1 2 1 + layer metal1 2 3 2 1 + layer poly 10 10 11 1 + contact m3contact metal3 metal2 5 + contact m2contact metal2 metal1 6 + contact pcontact metal1 poly 7 + notactive poly pcontact + +style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 + +end + +drc + width nwell 12 \ + "N-well width < 12 (Mosis #1.1)" + + width rnw 12 \ + "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" + + width pwell 12 \ + "P-well width < 12 (Mosis #1.1)" + + width diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 \ + "Diffusion width < 3 (Mosis #2.1)" + + width poly,fp,rp,pc/a,nfet,pfet,fet 2 \ + "Poly width < 2 (Mosis #3.1)" + + width nselect 2 \ + "N-Select width < 2 (Mosis #4.4)" + + width pselect 2 \ + "P-Select width < 2 (Mosis #4.4)" + + width pc/m1 4 \ + "Poly contact width < 4 (Mosis #5.1)" + + + width gc 2 \ + "GC contact width < 2 (Mosis #6.1)" + + width ndc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width nsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width pdc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width psc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ + "Metal1 width < 3 (Mosis #7.1)" + + width gv1 2 \ + "GV1 via width < 2 (Mosis #8.1)" + + width m2c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + + + + + + + width p2m12c 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + width p2m12c 4 \ + "stacked p2m12c width < 4 (Mosis #8.1)" + + width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ + "Metal2 width < 3 (Mosis #9.1)" + + width poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c 5 \ + "Poly2 width < 5 (Mosis #11.1)" + + width gc2 2 \ + "Generic contact2 width < 2 (Mosis #13.1)" + + width p2c 4 \ + "Poly2 contact width < 4 (Mosis #13.1)" + + width p2m12c 4 \ + "Poly2 contact width < 4 (Mosis #13.1)" + + width gv2 2 \ + "GV2 via width < 2 (Mosis #14.1)" + + width m3c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + + width m3,fm3,rm3,m3c/m3,pad 5 \ + "Metal3 width < 5 (Mosis #15.1)" + + width hr,phr 4 \ + "High-Resist width < 4 (Mosis #27.1)" + + width phr 5 \ + "High-Resist poly2R width < 5 (Mosis #27.7)" + + width nfi,pfi 4 \ + "N/P_field-implant width < 4 (Mosis #29.1)" + + spacing nwell nwell 6 touching_ok \ + "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing pwell pwell 6 touching_ok \ + "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing rnw nwell 18 touching_illegal \ + "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ + "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 touching_ok \ + "Diffusion spacing < 3 (Mosis #2.2)" + + spacing nwell ndiff,rnd,nfet,ndc/a 6 touching_illegal \ + "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" + + spacing pwell pdiff,rpd,pfet,pdc/a 6 touching_illegal \ + "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" + + spacing ndiff,rnd,nfet,ndc/a pdiff,rpd,pfet,pdc/a 12 touching_illegal \ + "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" + + edge4way ~(nwell)/well nwell 6 ~(pdiff,rpd,pfet,pdc/a)/active nwell 6 \ + "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 6 ~(ndiff,rnd,nfet,ndc/a)/active pwell 6 \ + "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(nwell)/well nwell 3 ~(nsd,nsc/a)/active nwell 3 \ + "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ + "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active + + spacing ndiff,rnd,ndc/a nsd,nsc/a 9 touching_illegal \ + "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing pdiff,rpd,pdc/a psd,psc/a 9 touching_illegal \ + "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing nwell psd,psc/a 3 touching_illegal \ + "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" + + spacing pwell nsd,nsc/a 3 touching_illegal \ + "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" + + spacing psd,psc/a rnw,prnw 3 touching_illegal \ + "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" + + spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ + "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" + + spacing ndiff,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ + "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" + + spacing pdiff,rpd,pfet,pdc/a,pfet nsd,nsc/a 4 touching_ok \ + "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" + + spacing poly,rp,pc/a,nfet,pfet,fet poly,rp,pc/a,nfet,pfet,fet 3 touching_ok \ + "Poly spacing < 3 (Mosis #3.2)" + + spacing poly,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ + "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" + + spacing fp fp 4 touching_ok \ + "Poly fill layer (fp) spacing < 4 (Mosis #0)" + + edge4way nfet,pfet,fet space/active,poly,fp,rp,pc/a 2 poly,fp,rp,pc/a 0 0 \ + "Poly overhang of Transistor < 2 (Mosis #3.3)" active + + edge4way nfet,pfet,fet space/active,ndiff,rnd,ndc/a,pdiff,rpd,pdc/a 3 ndiff,rnd,ndc/a,pdiff,rpd,pdc/a,nfet,pfet,fet 0 0 \ + "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active + + edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + "Poly spacing to Diffusion < 1 (Mosis #3.5)" + + edge4way nfet ~(nfet)/active 3 ~(pselect)/select ~(nfet)/active 3 \ + "N-Transistor space to P-Select < 3 (Mosis #4.1)" select + + edge4way pfet ~(pfet)/active 3 ~(nselect)/select ~(pfet)/active 3 \ + "P-Transistor space to N-Select < 3 (Mosis #4.1)" select + + edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ + "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active + + edge4way pfet ~(pfet)/active 3 ~(nsd,nsc/a)/active ~(pfet)/active 2 \ + "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active + +#PEZ edge4way psd,psc/a space ~(nfet)/active space \ +#PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active + +#PEZ edge4way nsd,nsc/a space ~(pfet)/active space \ +#PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active + + edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ + "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active + + edge4way space nselect,pselect 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active + + edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active + + edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active + + edge4way space nselect,pselect 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active + + edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active + + edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active + + edge4way diff space 2 nselect space 2 \ + "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way diff space 2 pselect space 2 \ + "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way ndiff,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ + "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select + + edge4way pdiff,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ + "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select + + edge4way ~(pdiff,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ + "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select + + edge4way ~(ndiff,rnd,nfet,ndc/a,nsd,nsc/a)/active ndiff,rnd,nfet,ndc/a,nsd,nsc/a 1 ~(pselect)/select 0 0 \ + "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select + + width nsd,nsc/a,psd,psc/a 2 \ + "N-Ohmic,P-Ohmic width < 2 (Mosis #4.1)" + + spacing nselect nselect 2 touching_ok \ + "N-Select spacing < 2 (Mosis #4.4)" + + spacing pselect pselect 2 touching_ok \ + "P-Select spacing < 2 (Mosis #4.4)" + + edge4way ndiff,rnd,ndc/a psd,psc/a 2 ~(ndiff,rnd,ndc/a)/active 0 0 \ + "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" + + edge4way pdiff,rpd,pdc/a nsd,nsc/a 2 ~(pdiff,rpd,pdc/a)/active 0 0 \ + "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" + + edge4way gc ~(gc)/contact 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a ~(gc)/contact 1 \ + "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active + + edge4way gc space 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a space 1 \ + "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active + + edge4way ~(poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ + "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact + + spacing gc gc 3 touching_ok \ + "Generic contact spacing < 3 (Mosis #5.3)" + + edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 + + edge4way ~(gc2)/contact gc2 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + "Generic contact2 cannot touch Metal1 contacts (Mosis #0)" metal1 + + spacing gv1 m2c/m2 2 touching_illegal \ + "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" + + spacing poly,fp,rp,pc/a pc/a 4 touching_ok \ + "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" + + edge4way gc ~(gc)/contact 1 diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,poly,fp,rp,pc/a ~(gc)/contact 1 \ + "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active + + spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" + + spacing nsc/m1 pdc/m1 1 touching_illegal \ + "nsc spacing to pdc < 1 (Mosis #6.3)" + + spacing psc/m1 ndc/m1 1 touching_illegal \ + "psc spacing to ndc < 1 (Mosis #6.3)" + + + + + + + + spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 1 touching_illegal \ + "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" + + spacing nfet,pfet gc 2 touching_illegal \ + "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ + "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" + + spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 4 touching_ok \ + "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" + + spacing pc/a ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" + + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ + "Metal1 spacing < 3 (Mosis #7.2)" + + spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ + "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" + + spacing fm1 fm1 4 touching_ok \ + "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" + + edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ + "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact + + spacing gv1 gv1 3 touching_ok \ + "GV1 via spacing < 3 (Mosis #8.2)" + + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ + "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 + + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ + "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 + + spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ + "Metal2 spacing < 3 (Mosis #9.2)" + + spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ + "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" + + spacing fm2 fm2 4 touching_ok \ + "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" + + edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ + "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 + + width glass 10 \ + "COG width < 10 (Mosis #10.2)" + + edge4way ~(pad)/metal3 pad 20 ~(glass)/oxide pad 20 \ + "pad overlap of COG < 20 (Mosis #10.3)" oxide + + spacing ecap ecap 3 touching_ok \ + "Ecap spacing < 3 (Mosis #11.2)" + + edge4way ecap ~(ecap)/cap 5 poly,fp,rp,pc/a ~(ecap)/cap 5 \ + "Poly overlap of Ecap < 5 (Mosis #11.3)" active + + edge4way ~(ecap)/cap ecap 1 poly,fp,rp,pc/a 0 0 \ + "Ecap must touch Poly (Mosis #11.3x)" active + + edge4way poly2,phr,p2c,p2m12c space 5 ~(poly,fp,rp,pc/a)/active space 5 \ + "Poly2 spacing to Poly < 5 (Mosis #11.3c)" active + + spacing ecap pc/a 2 touching_illegal \ + "Ecap spacing to Poly contact < 2 (Mosis #11.5)" + + spacing ecap gc 3 touching_illegal \ + "Ecap spacing to Generic contact < 3 (Mosis #11.5)" + + spacing poly2,ecap,phr,p2c,p2m12c poly2,ecap,phr,p2c,p2m12c 3 touching_ok \ + "Poly2 spacing < 3 (Mosis #11.2)" + + spacing poly2,ecap,phr,p2c,p2m12c pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ + "Poly2 spacing to Poly contact,Diffusion contact < 2 (Mosis #11.5)" + + spacing poly2,ecap,phr,p2c,p2m12c gc,gc 3 touching_illegal \ + "Poly2 spacing to GC contact < 3 (Mosis #11.5)" + + spacing gc2 gc2 3 touching_ok \ + "Generic contact2 spacing < 3 (Mosis #13.2)" + + edge4way ~(ecap)/cap ecap 3 ~(gc2)/contact ecap 3 \ + "Ecap overlap of Generic contact2 < 3 (Mosis #13.3)" contact + + edge4way ~(ecap)/cap ecap 2 ~(p2c,p2m12c)/cap ecap 2 \ + "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" cap + + edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap Generic contact2 by 1 (Mosis #13.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc2)/contact 0 0 \ + "Metal1(edge) cannot touch Generic contact2 (Mosis #13.4)" contact + + edge4way ~(poly2,ecap,phr,p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 ~(p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 \ + "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" cap + + spacing gv2 gv2 3 touching_ok \ + "GV2 via spacing < 3 (Mosis #14.2)" + + spacing gv2 m3c/m2 2 touching_illegal \ + "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" + + edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ + "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 + + spacing m3,rm3,m3c/m3,pad m3,rm3,m3c/m3,pad 3 touching_ok \ + "Metal3 spacing < 3 (Mosis #15.2)" + + spacing m3,rm3,m3c/m3,pad fm3,fapm 3 touching_illegal \ + "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" + + spacing fm3 fm3 4 touching_ok \ + "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" + + edge4way m3c/m2 ~(m3c/m2)/metal2 1 m3,fm3,rm3,m3c/m3,pad ~(m3c/m2)/metal2 1 \ + "Metal3 overlap of Metal3 contact < 1 (Mosis #15.3)" metal3 + + edge4way gv2 space 2 m3,fm3,rm3,m3c/m3,pad space 2 \ + "Metal3 must overlap GV2 via by 2 (Mosis #15.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,pad)/metal3 m3,fm3,rm3,m3c/m3,pad 1 ~(gv2)/via2 0 0 \ + "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 + + spacing hr,phr hr,phr 4 touching_ok \ + "High-Resist spacing < 4 (Mosis #27.2)" + + spacing hr,phr,phr p2c,p2m12c 2 touching_illegal \ + "High-Resist spacing to Poly2 contact < 2 (Mosis #27.3)" + + spacing hr,phr,phr gc 2 touching_illegal \ + "High-Resist spacing to GC contact < 2 (Mosis #27.3)" + + edge4way hr,phr space 2 ~(ndiff,rnd,ndc/a,pdiff,rpd,pdc/a)/active 0 2 \ + "High-Resist space to Diffusion < 2 (Mosis #27.4)" active + + spacing hr,phr,phr poly2,ecap,phr,p2c,p2m12c 2 touching_ok \ + "High-Resist spacing to other Poly2 < 2 (Mosis #27.5)" + + edge4way hr,phr space 2 ~(poly2,ecap,phr,p2c,p2m12c)/contact hr,phr 2 \ + "High-Resist space to Poly2 < 2 (Mosis #27.5x)" contact + + spacing nwell phr 4 touching_illegal \ + "N-well spacing to Silicide-Block poly2R < 4 (Mosis #27.6)" + + spacing phr phr 7 touching_ok \ + "High-Resist poly2R spacing < 7 (Mosis #27.13)" + + edge4way phr space/active,hr 2 hr hr 2 \ + "High-Resist overlap of High-Resist poly2R < 2 (Mosis #27.15)" + + spacing nfi nfi 4 touching_ok \ + "N_field-implant spacing < 4 (Mosis #35.2)" + + spacing pfi pfi 4 touching_ok \ + "P_field-implant spacing < 4 (Mosis #35.2)" + + spacing nfi pfi 4 touching_illegal \ + "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" + + spacing nwell,pdiff,rpd,pfet,pdc/a pfi 4 touching_illegal \ + "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" + + spacing pwell,ndiff,rnd,nfet,ndc/a nfi 4 touching_illegal \ + "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" + + edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ + "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant + + edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ + "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant + + spacing fa fapm 4 touching_illegal \ + "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" + + width fa 7 \ + "filla width < 7 (Mosis #0)" + + width fapm 7 \ + "fillapm width < 7 (Mosis #0)" + + width fp 7 \ + "fillp width < 7 (Mosis #0)" + + width fm1 7 \ + "fillm1 width < 7 (Mosis #0)" + + width fm2 7 \ + "fillm2 width < 7 (Mosis #0)" + + width fm3 7 \ + "fillm3 width < 7 (Mosis #0)" + + edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way rp space/active 1 prp 0 0 \ + "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rp2 space/cap 1 prp2 0 0 \ + "prp2 overhang of rpoly2 (for resistor L/W extraction) < 1 (Mosis #0)" cap + + edge4way rnw space/active 1 prnw 0 0 \ + "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rpd space/active 1 prpd 0 0 \ + "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnd space/active 1 prnd 0 0 \ + "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rm1 space/metal1 1 prm1 0 0 \ + "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 + + edge4way rm2 space/metal2 1 prm2 0 0 \ + "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 + + edge4way rm3 space/metal3 1 prm3 0 0 \ + "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 + + edge4way ndc/a,nsc/a ~(ndc/a,nsc/a)/active 1 ~(ndc/a,nsc/a)/active (~(ndc/a,nsc/a),ndc/a,nsc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc2 ~(gc2)/contact 1 ~(gc2)/contact (~(gc2),gc2)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way p2c,p2m12c ~(p2c,p2m12c)/cap 1 ~(p2c,p2m12c)/cap (~(p2c,p2m12c),p2c,p2m12c)/cap 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,gc,pc/a,gc + + exact_overlap gc2,p2c,p2m12c + + edge4way pad ~(pad)/m3 1 ~(pad)/m3 (~(pad),pad)/m3 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1 + + exact_overlap m2c/m2 + + exact_overlap m3c/m3 + + exact_overlap gv1 + + exact_overlap gv2 + + + width m1p 4 \ + "Metal1 PIN width < 4 (do_pins)" + + spacing m1p m1p 4 touching_ok \ + "Metal1 PIN spacing < 4 (do_pins)" + + width m2p 4 \ + "Metal2 PIN width < 4 (do_pins)" + + spacing m2p m2p 4 touching_ok \ + "Metal2 PIN spacing < 4 (do_pins)" + + width m3p 6 \ + "Metal3 PIN width < 6 (do_pins)" + + spacing m3p m3p 4 touching_ok \ + "Metal3 PIN spacing < 4 (do_pins)" + +#CC cifstyle lambda=0.30(p) +#CC cifwidth CWN 360 \ +#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" +#CC cifspacing CWN CWN 180 touching_ok \ +#CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" +#CC cifwidth CWP 360 \ +#CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" +#CC cifspacing CWP CWP 180 touching_ok \ +#CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" +#CC cifwidth CSN 60 \ +#CC "generated CIF layer CSN width will be < 2 (';cif see CSN')" +#CC cifspacing CSN CSN 60 touching_ok \ +#CC "generated CIF layer CSN spacing will be < 2 (';cif see CSN')" +#CC cifwidth CSP 60 \ +#CC "generated CIF layer CSP width will be < 2 (';cif see CSP')" +#CC cifspacing CSP CSP 60 touching_ok \ +#CC "generated CIF layer CSP spacing will be < 2 (';cif see CSP')" + + stepsize 400 + +end + +#--------------------------------------------------- +# LEF format definitions +#--------------------------------------------------- + +lef + +ignore PC +ignore CA + +routing m1 M1 m1 met1 +routing m2 M2 m2 met2 +routing m3 M3 m3 met3 + +contact m2c via via1 V1 v1 +contact m3c via2 V2 v2 + +end + +extract + style AMI0.5um(amic5)from:T24H + cscale 1 + lambda 30 + step 100 + sidehalo 8 + planeorder well 0 + planeorder implant 1 + planeorder select 2 + planeorder cap 3 + planeorder active 4 + planeorder metal1 5 + planeorder metal2 6 + planeorder metal3 7 + planeorder oxide 8 + planeorder xp 9 + planeorder comment 10 + planeorder contact 11 + planeorder via1 12 + planeorder via2 13 + planeorder fill 14 + + resist (ndiff,rnd,ndc,nsd,nsc)/active 82200 + resist (pdiff,rpd,pdc,psd,psc)/active 105200 + resist (nwell)/well 808000 + resist (rnw)/active 808000 + resist (pwell)/well 1 + resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22000 + resist (poly2,ecap,p2c,p2m12c,p2c,p2m12c)/cap 40300 + resist (phr)/cap 40300 + resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c,m2c)/metal1 90 + resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 + resist (m3,fm3,rm3,m3c,pad)/metal3 50 + + contact ndc 4 62700 + contact pdc 4 160000 + contact pc 4 15600 + contact p2c 4 26100 + contact m2c 4 910 + contact m3c 4 830 + + +#poly2 + overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c)/cap 84.960 + +#nwell,cwell,pwell + areacap (nwell)/well 3.600 + +#rnw + areacap (rnw)/active 3.600 + +#ndiff +# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.430 +# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.430 +# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 94.800 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 94.800 + + areacap (rnd)/active 38.430 + overlap (rnd)/active ~space/w 38.430 + perimc (rnd)/active ~(rnd)/active 94.800 + sideoverlap (rnd)/active ~(rnd)/active ~space/w 94.800 + +#pdiff +# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.880 +# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.880 +# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 75.300 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 75.300 + + areacap (rpd)/active 65.880 + overlap (rpd)/active ~space/w 65.880 + perimc (rpd)/active ~(rpd)/active 75.300 + sideoverlap (rpd)/active ~(rpd)/active ~space/w 75.300 + +#rnw + +#poly +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 221.670 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 58.500 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 213.480 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 82.800 + + areacap (poly,fp,rp,pc)/active 7.740 + overlap (poly,fp,rp,pc)/active ~space/w 7.740 + +#poly2 + +#rnw + +#metal1 + areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.700 + +#metal1-sub blocked by ~space/a,~space/c + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.700 ~space/a,~space/c + perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.700 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 20.700 ~space/a,~space/c + +#rnw + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 2.700 ~space/c + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 20.700 ~space/c + +#metal1-diff blocked by ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 20.700 ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 20.700 ~space/c + +#metal1-poly blocked by ~space/c + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.590 ~space/c + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 15.900 ~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 15.900 ~space/c + +#metal1-poly2 not blocked + overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly2,ecap,phr,p2c,p2m12c)/cap 3.960 + +#metal2 + areacap (m2,fm2,rm2,m3c)/metal2 1.350 + +#metal2-sub blocked by + overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.350 ~space/a,~space/m1,~space/c + perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 15.900 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 15.900 ~space/a,~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 15.900 ~space/m1,~space/c + +#metal2-*diff blocked by ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 15.900 ~space/m1,~space/c + overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 15.900 ~space/m1,~space/c + +#metal2-poly blocked by ~space/m1,~space/c + overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 1.350 ~space/m1,~space/c + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 10.800 ~space/m1,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 10.800 ~space/m1,~space/c + +#metal2-poly2 blocked by ~space/m1 + +#M2->M1 + overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 2.520 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 14.700 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 14.700 + +#metal3 + areacap (m3,fm3,rm3,pad)/metal3 0.900 + +#metal3-sub blocked by ~space/a,~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 ~space/w 0.900 ~space/a,~space/m1,~space/m2,~space/c + perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 10.500 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 10.500 ~space/a,~space/m1,~space/m2,~space/c + +#rnw + overlap (m3,fm3,rm3,pad)/metal3 rnw/active 0.900 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 10.500 ~space/m1,~space/m2,~space/c + +#metal3-*diff blocked by ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (ndiff,rnd,ndc)/active 0.990 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 10.500 ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (pdiff,rpd,pdc)/active 0.990 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 10.500 ~space/m1,~space/m2,~space/c + +#metal3-poly blocked by ~space/m1,~space/m2,~space/c + overlap (m3,fm3,rm3,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 0.810 ~space/m1,~space/m2,~space/c + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.100 ~space/m1,~space/m2,~space/c + sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.100 ~space/m1,~space/m2,~space/c + +#metal3-poly2 blocked by ~space/m1,~space/m2 + +#M3->M1 + overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 1.080 ~space/m2 + +#metal3-metal1 blocked by ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 9.900 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.900 ~space/m2 + +#M3->M2 + overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 3.060 + sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 16.800 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 16.800 + +#metal4 + +#metal5 + +#metal6 + +#metal7 + +#metali + +#fets + +# fet pfet pdiff,pdc 2 pfet Vdd! nwell 83 213 +# fet pfet pdiff,pdc 1 pfet Vdd! nwell 83 213 + + device mosfet pfet pfet pdiff,pdc nwell $VDD 83 213 + +# fet nfet ndiff,ndc 2 nfet Gnd! pwell 59 222 +# fet nfet ndiff,ndc 1 nfet Gnd! pwell 59 222 + + device mosfet nfet nfet ndiff,ndc pwell $GND 59 222 + + fetresis pfet linear 20996 + fetresis pfet saturation 20996 + fetresis nfet linear 6144 + fetresis nfet saturation 6144 + +# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 +# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 +# fet rpoly2 poly2,p2c 2 poly2Resistor Gnd! nwell,pwell 0 0 +# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 +# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 + + device resistor None rnwell nsd,nsc + device resistor None rpoly poly,pc + device resistor None rpoly2 poly2,p2c + device resistor None rndiff ndiff,ndc + device resistor None rpdiff pdiff,pdc + +# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 +# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 +# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 +# fet phr poly2,p2c 2 phrResistor Gnd! nwell,pwell 0 0 + + device resistor None rmetal1 *metal1 + device resistor None rmetal2 *metal2 + device resistor None rmetal3 *metal3 + device resistor None phr poly2,p2c + +end + +wiring + contact pdcontact 4 metal1 0 pdiff 0 + contact ndcontact 4 metal1 0 ndiff 0 + contact pcontact 4 metal1 0 poly 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 1 + +end + +router + layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,rp,ndiff,rnd,nsd,pdiff,rpd,psd,m1,fm1,rm1 1 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 + contacts m2contact 4 + gridspacing 8 + +end + +plowing + fixed nfet,pfet,glass,pad + covered nfet,pfet + drag nfet,pfet + +end + +plot +style colorversatec + ndiff,rnd,ndc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + ndiff,rnd,ndc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + nsd,nsc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + nsd,nsc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + pdiff,rpd,pdc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + pdiff,rpd,pdc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + pdiff,rpd,pdc/a magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + psd,psc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + psd,psc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + psd,psc/a magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + poly,fp,rp,pc/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + poly2,ecap,phr,p2c,p2m12c yellow \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + m2c/m1,gv1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + m3c/m2,gv2 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + m3c/m2,gv2 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + m3c/m2,gv2 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + m3c/m2,gv2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X + +style versatec + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + gv1 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + poly,fp,rp,pc/a,nfet,pfet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + nsd,nsc/a \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + m2,fm2,rm2,m2c/m2,m3c/m2 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + pdiff,rpd,pdc/a,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + psd,psc/a \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + ndiff,rnd,ndc/a,nfet \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X + +style gremlin + pfet 9 + nfet 10 + gv1 11 + pwell 15 + nwell 16 + poly,fp,rp,pc/a,nfet,pfet 19 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc 22 + pad,glass 23 + nsd,nsc/a 24 + gv1 28 + pdiff,rpd,pdc/a,pfet 29 + psd,psc/a 30 + ndiff,rnd,ndc/a,nfet 31 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc,gv1 X + +end + From e3f2ee8a7e10c315e179f65edd44e40eda777a7e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 15 Aug 2018 14:19:04 -0700 Subject: [PATCH 9/9] Fix VCG error in channel route. Note, the channel routing algorithm still does not handle horizontal conflicts or cyclic vertical conflicts! --- compiler/base/hierarchy_layout.py | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index b5a0f3fd..6bf59ea2 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -718,7 +718,7 @@ class layout(lef.lef): conflicts between pins. """ - def remove_pin_from_graph(pin, g): + def remove_net_from_graph(pin, g): # Remove the pin from the keys g.pop(pin,None) # Remove the pin from all conflicts @@ -726,7 +726,8 @@ class layout(lef.lef): for other_pin,conflicts in g.items(): if pin in conflicts: conflicts.remove(pin) - vcg[other_pin]=conflicts + g[other_pin]=conflicts + return g if not pitch: pitch = self.m2_pitch @@ -740,20 +741,24 @@ class layout(lef.lef): # Initialize the vertical conflict graph (vcg) and make a list of all pins vcg = {} - for (top_name, bot_name) in route_map: - vcg[top_name] = [] - vcg[bot_name] = [] # Find the vertical pin conflicts # FIXME: O(n^2) but who cares for now for top_name,top_pin in top_pins.items(): + vcg[top_name]=[] for bot_name,bot_pin in bottom_pins.items(): - if not vertical and abs(top_pin.center().x-bot_pin.center().x) < pitch: - vcg[top_name].append(bot_name) - vcg[bot_name].append(top_name) - elif vertical and abs(top_pin.center().y-bot_pin.center().y) < pitch: - vcg[top_name].append(bot_name) - vcg[bot_name].append(top_name) + # Remember, vertical is the boolean of the routes in the channel + # so check the intervals of the pins in the other dimension + x_overlap = abs(top_pin.center().x-bot_pin.center().x)