diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index e5eb3043..820adcce 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -30,8 +30,8 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base): props.bitcell.cell_1rw1r.pin.vdd, props.bitcell.cell_1rw1r.pin.gnd] - type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", - "INPUT", "INPUT", "POWER", "GROUND"] + type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", + "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] (width, height) = utils.get_libcell_size("cell_1rw_1r", GDS["unit"], diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 477100fe..6ceff7ca 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -48,8 +48,11 @@ class bitcell_base_array(design.design): # Make a flat list too self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl] - def create_all_wordline_names(self, remove_num_wordlines=0): - for row in range(self.row_size - remove_num_wordlines): + def create_all_wordline_names(self, row_size=None): + if row_size == None: + row_size = self.row_size + + for row in range(row_size): for port in self.all_ports: self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 392f573c..24ecc640 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -26,7 +26,13 @@ class col_cap_array(bitcell_base_array): def create_netlist(self): """ Create and connect the netlist """ # This will create a default set of bitline/wordline names - self.create_all_wordline_names() + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + + if not end_caps_enabled: + self.create_all_wordline_names() self.create_all_bitline_names() self.add_modules() @@ -63,7 +69,7 @@ class col_cap_array(bitcell_base_array): indexed by column and row, for instance use in bitcell_array """ - if len(self.ports) == 1: + if len(self.all_ports) == 1: pin_name = cell_properties.bitcell.cell_6t.pin bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col), "{0}_{1}".format(pin_name.br0, col), diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 7024a6fc..9fde2a67 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -85,25 +85,15 @@ class dummy_array(bitcell_base_array): height=self.height) wl_names = self.cell.get_all_wl_names() - if not props.compare_ports(props.bitcell.split_wl): - for row in range(self.row_size): - for port in self.all_ports: - wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port]) + for row in range(self.row_size): + for port in self.all_ports: + wl_pins = self.cell_inst[row, 0].get_pins(wl_names[port]) + for wl_pin in wl_pins: self.add_layout_pin(text="wl_{0}_{1}".format(port, row), layer=wl_pin.layer, offset=wl_pin.ll().scale(0, 1), width=self.width, height=wl_pin.height()) - else: - for row in range(self.row_size): - for port in self.all_ports: - for wl in range(len(wl_names)): - wl_pin = self.cell_inst[row, 0].get_pin("wl{}".format(wl)) - self.add_layout_pin(text="wl{0}_{1}_{2}".format(wl, port, row), - layer=wl_pin.layer, - offset=wl_pin.ll().scale(0, 1), - width=self.width, - height=wl_pin.height()) # Copy a vdd/gnd layout pin from every cell for row in range(self.row_size): @@ -112,7 +102,6 @@ class dummy_array(bitcell_base_array): for pin_name in ["vdd", "gnd"]: self.copy_layout_pin(inst, pin_name) - def input_load(self): # FIXME: This appears to be old code from previous characterization. Needs to be updated. wl_wire = self.gen_wl_wire() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 0814728f..0444a2cc 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -59,9 +59,19 @@ class replica_bitcell_array(bitcell_base_array): "Invalid number of RBLs for port configuration.") # Two dummy rows plus replica even if we don't add the column - self.extra_rows = 2 + sum(self.rbl) + self.extra_rows = sum(self.rbl) # Two dummy cols plus replica if we add the column - self.extra_cols = 2 + len(self.left_rbl) + len(self.right_rbl) + self.extra_cols = len(self.left_rbl) + len(self.right_rbl) + + + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + # If we aren't using row/col caps, then we need to use the bitcell + if not end_caps_enabled: + self.extra_rows += 2 + self.extra_cols += 2 self.create_netlist() if not OPTS.netlist_only: @@ -184,7 +194,7 @@ class replica_bitcell_array(bitcell_base_array): # + left replica column(s) # + bitcell columns # + right replica column(s) - column_offset = 1 + len(self.left_rbl) + self.column_size + self.rbl[0], + column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0], rows=self.row_size + self.extra_rows, mirror=(self.rbl[0] + 1) %2) self.add_mod(self.row_cap_right) @@ -230,6 +240,11 @@ class replica_bitcell_array(bitcell_base_array): self.add_pin_list(self.rbl_bitline_names[port], "INOUT") def add_wordline_pins(self): + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + # Wordlines to ground self.gnd_wordline_names = [] @@ -245,7 +260,6 @@ class replica_bitcell_array(bitcell_base_array): self.wordline_names = self.bitcell_array.wordline_names self.all_wordline_names = self.bitcell_array.all_wordline_names - # All wordlines including dummy and RBL self.replica_array_wordline_names = [] self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names())) @@ -296,19 +310,19 @@ class replica_bitcell_array(bitcell_base_array): self.dummy_row_insts = [] self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", mod=self.col_cap_bottom)) - self.connect_inst(["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies) + self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies) self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", mod=self.col_cap_top)) - self.connect_inst(["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies) + self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies) # Left/right Dummy columns self.dummy_col_insts = [] self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", mod=self.row_cap_left)) - self.connect_inst(self.replica_array_wordline_names + self.supplies) + self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies) self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", mod=self.row_cap_right)) - self.connect_inst(self.replica_array_wordline_names + self.supplies) + self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies) def create_layout(self): diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 3d6b524b..d7e36fce 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -28,8 +28,13 @@ class replica_column(bitcell_base_array): self.right_rbl = rbl[1] self.replica_bit = replica_bit # left, right, regular rows plus top/bottom dummy cells - self.total_size = self.left_rbl + rows + self.right_rbl + 2 - + self.total_size = self.left_rbl + rows + self.right_rbl + try: + if not cell_properties.bitcell.end_caps: + self.total_size += 2 + except AttributeError: + self.total_size += 2 + self.column_offset = column_offset debug.check(replica_bit != 0 and replica_bit != rows, @@ -62,14 +67,7 @@ class replica_column(bitcell_base_array): def add_pins(self): self.create_all_bitline_names() - try: - if cell_properties.bitcell.end_caps: - # remove 2 wordlines to account for top/bot - self.create_all_wordline_names(remove_num_wordlines=2) - else: - self.create_all_wordline_names() - except AttributeError: - self.create_all_wordline_names() + self.create_all_wordline_names(self.total_size) self.add_pin_list(self.all_bitline_names, "OUTPUT") self.add_pin_list(self.all_wordline_names, "INPUT") @@ -91,7 +89,6 @@ class replica_column(bitcell_base_array): # Used for pin names only self.cell = factory.create(module_type="bitcell") - def create_instances(self): self.cell_inst = {} try: @@ -106,22 +103,22 @@ class replica_column(bitcell_base_array): # Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell. if (row > self.left_rbl and row < self.total_size - self.right_rbl - 1): self.cell_inst[row]=self.add_inst(name=name, - mod=self.replica_cell) + mod=self.replica_cell) self.connect_inst(self.get_bitcell_pins(row, 0)) elif row==self.replica_bit: self.cell_inst[row]=self.add_inst(name=name, - mod=self.replica_cell) + mod=self.replica_cell) self.connect_inst(self.get_bitcell_pins(row, 0)) elif (row == 0 or row == self.total_size - 1): self.cell_inst[row]=self.add_inst(name=name, - mod=self.edge_cell) + mod=self.edge_cell) if end_caps_enabled: self.connect_inst(self.get_bitcell_pins_col_cap(row, 0)) else: self.connect_inst(self.get_bitcell_pins(row, 0)) else: self.cell_inst[row]=self.add_inst(name=name, - mod=self.dummy_cell) + mod=self.dummy_cell) self.connect_inst(self.get_bitcell_pins(row, 0)) def place_instances(self): @@ -153,8 +150,7 @@ class replica_column(bitcell_base_array): dir_key = "" self.cell_inst[row].place(offset=offset, - mirror=dir_key) - + mirror=dir_key) def add_layout_pins(self): """ Add the layout pins """