From 20b869f8e166c20ec36bfe7a9b4845965d0efb38 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 11 Jan 2019 14:16:57 -0800 Subject: [PATCH] Remove tabs --- compiler/base/verilog.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 7d713eca..a2ddcadf 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -75,14 +75,14 @@ class verilog: """ Create the input regs for the given port. """ - self.vf.write(" reg csb{0}_reg;\n".format(port)) + self.vf.write(" reg csb{0}_reg;\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" reg web{0}_reg;\n".format(port)) - self.vf.write(" reg [ADDR_WIDTH-1:0] ADDR{0}_reg;\n".format(port)) + self.vf.write(" reg web{0}_reg;\n".format(port)) + self.vf.write(" reg [ADDR_WIDTH-1:0] ADDR{0}_reg;\n".format(port)) if port in self.write_ports: - self.vf.write(" reg [DATA_WIDTH-1:0] DIN{0}_reg;\n".format(port)) + self.vf.write(" reg [DATA_WIDTH-1:0] DIN{0}_reg;\n".format(port)) if port in self.read_ports: - self.vf.write(" reg [DATA_WIDTH-1:0] DOUT{0};\n".format(port)) + self.vf.write(" reg [DATA_WIDTH-1:0] DOUT{0};\n".format(port)) def add_flops(self, port): """ @@ -120,10 +120,10 @@ class verilog: """ Add the module input and output declaration for a port. """ - self.vf.write(" input clk{0}; // clock\n".format(port)) - self.vf.write(" input csb{0}; // active low chip select\n".format(port)) + self.vf.write(" input clk{0}; // clock\n".format(port)) + self.vf.write(" input csb{0}; // active low chip select\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" input web{0}; // active low write control\n".format(port)) + self.vf.write(" input web{0}; // active low write control\n".format(port)) self.vf.write(" input [ADDR_WIDTH-1:0] ADDR{0};\n".format(port)) if port in self.write_ports: self.vf.write(" input [DATA_WIDTH-1:0] DIN{0};\n".format(port))