diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 001093dd..5ae2f26e 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -72,26 +72,28 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             self.lvs_write(tempspice)
             self.gds_write(tempgds)
             # Final verification option does not allow nets to be connected by label.
-            num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification)
-            num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
+            self.drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification)
+            self.lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
 
             # force_check is used to determine decoder height and other things, so we shouldn't fail
             # if that flag is set
             if OPTS.inline_lvsdrc and not force_check:
-                debug.check(num_drc_errors == 0,
+                debug.check(self.drc_errors == 0,
                             "DRC failed for {0} with {1} error(s)".format(self.name,
-                                                                          num_drc_errors))
-                debug.check(num_lvs_errors == 0,
+                                                                          self.drc_errors))
+                debug.check(self.lvs_errors == 0,
                             "LVS failed for {0} with {1} errors(s)".format(self.name,
-                                                                           num_lvs_errors))
+                                                                           self.lvs_errors))
 
             if OPTS.purge_temp:
                 os.remove(tempspice)
                 os.remove(tempgds)
             
-            return (num_drc_errors, num_lvs_errors)
         else:
-            return ("skipped", "skipped")
+            self.drc_errors = "skipped"
+            self.lvs_errors = "skipped"
+
+        return (self.drc_errors, self.lvs_errors)
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 92882db7..525f2180 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -658,11 +658,7 @@ class lib:
 
         # information of checks
         # run it only the first time
-        try:
-            datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors))
-        except AttributeError:
-            (self.drc_errors, self.lvs_errors) = self.sram.DRC_LVS(final_verification=True)
-            datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors))            
+        datasheet.write("{0},{1},".format(self.sram.drc_errors, self.sram.lvs_errors))
         
         # write area
         datasheet.write(str(self.sram.width * self.sram.height) + ',')
diff --git a/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py
new file mode 100644
index 00000000..a09edfdb
--- /dev/null
+++ b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py
@@ -0,0 +1,21 @@
+word_size = 4
+num_words = 64
+words_per_row = 2
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+nominal_corners_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+# route_supplies = True
+check_lvsdrc = True
+
+output_path = "temp"
+output_name = "sram_1rw_{0}_{1}_{2}".format(word_size,
+                                            num_words,
+                                            tech_name)
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 89ecfaaf..b16c28fa 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -129,7 +129,7 @@ class sram_base(design, verilog, lef):
 
         start_time = datetime.datetime.now()
         # We only enable final verification if we have routed the design
-        self.DRC_LVS(final_verification=OPTS.route_supplies)
+        self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=True)
         if not OPTS.is_unit_test:
             print_time("Verification", datetime.datetime.now(), start_time)