diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index c1ad33cd..89d49707 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -114,8 +114,6 @@ class control_logic(design.design):
             bitcell_loads = int(math.ceil(self.num_rows / 2.0))
             self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
             
-            self.set_sen_wl_delays()
-            
             if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
                 #This resizes to match fall and rise delays, can make the delay chain weird sizes.
                 # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds
index 00dc1855..5f3e7213 100644
Binary files a/technology/freepdk45/gds_lib/cell_1rw_1r.gds and b/technology/freepdk45/gds_lib/cell_1rw_1r.gds differ
diff --git a/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds b/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds
index 96bf3d75..cdb099ac 100644
Binary files a/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds and b/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds differ
diff --git a/technology/freepdk45/sp_lib/cell_1rw_1r.sp b/technology/freepdk45/sp_lib/cell_1rw_1r.sp
index 483a0b4b..f1c45604 100644
--- a/technology/freepdk45/sp_lib/cell_1rw_1r.sp
+++ b/technology/freepdk45/sp_lib/cell_1rw_1r.sp
@@ -6,8 +6,8 @@ MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
 MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q Q_bar gnd gnd NMOS_VTG W=270.0n L=50n m=1
-MM0 Q_bar Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
+MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
 MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
 MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
 .ENDS
diff --git a/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp b/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp
index 5c7fca51..d108b7bf 100644
--- a/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp
+++ b/technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp
@@ -6,8 +6,9 @@ MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1
 MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
 MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
 MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
-MM1 Q vdd gnd gnd NMOS_VTG W=270.0n L=50n m=1
-MM0 vdd Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
+MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1
+MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
 MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1
 MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1
 .ENDS
+