diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index ec0b4e96..055bf412 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -110,7 +110,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         """Initializes parameters relevant to the graph creation"""
         #Only initializes a set for checking instances which should not be added
         self.graph_inst_exclude = set()
-            
+    
     def build_graph(self, graph, inst_name, port_nets):        
         """Recursively create graph from instances in module."""
         
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 81b31ef8..c4afc8a1 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -247,7 +247,7 @@ class delay(simulation):
     def create_graph(self):
         """Creates timing graph to generate the timing paths for the SRAM output."""
         
-        self.sram.bank.bitcell_array.init_graph_params() # Removes previous bit exclusions
+        self.sram.bank.bitcell_array.bitcell_array.init_graph_params() # Removes previous bit exclusions
         self.sram.bank.bitcell_array.graph_exclude_bits(self.wordline_row, self.bitline_column)
         
         # Generate new graph every analysis as edges might change depending on test bit
@@ -1313,6 +1313,7 @@ class delay(simulation):
             for load in loads:
                 # Calculate delay based on slew and load
                 path_delays = self.graph.get_timing(bl_path, self.corner, slew, load)
+                
                 total_delay = self.sum_delays(path_delays)
                 max_delay = max(max_delay, total_delay.delay)
                 debug.info(1,'{}, {}, {}, {}'.format(slew,load,total_delay.delay/1e3, total_delay.slew/1e3))
diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py
index 8c92440c..e77d577f 100644
--- a/compiler/modules/sense_amp.py
+++ b/compiler/modules/sense_amp.py
@@ -42,7 +42,7 @@ class sense_amp(design.design):
         # Default is 8x. Per Samira and Hodges-Jackson book:
         # "Column-mux transistors driven by the decoder must be sized for optimal speed"
         bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
-        return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff   
+        return spice["min_tx_drain_c"]*(bitline_pmos_size)#ff   
         
     def get_stage_effort(self, load):
         #Delay of the sense amp will depend on the size of the amp and the output load.
diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py
index 3b43e789..114f0c6e 100755
--- a/compiler/tests/21_model_delay_test.py
+++ b/compiler/tests/21_model_delay_test.py
@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-@unittest.skip("SKIPPING 21_model_delay_test")
+# @unittest.skip("SKIPPING 21_model_delay_test")
 class model_delay_test(openram_test):
     """ Compare the accuracy of the analytical model with a spice simulation. """
     
@@ -51,23 +51,28 @@ class model_delay_test(openram_test):
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
+     
+        # Run a spice characterization
         spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
         spice_data.update(port_data[0])
      
+        # Run analytical characterization
         model_data, port_data = d.analytical_delay(slews, loads)
         model_data.update(port_data[0])
         
-        #Only compare the delays
+        # Only compare the delays
         spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
         model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
         debug.info(1,"Spice Delays={}".format(spice_delays))
         debug.info(1,"Model Delays={}".format(model_delays))
+        
         if OPTS.tech_name == "freepdk45":
             error_tolerance = 0.25
         elif OPTS.tech_name == "scn4m_subm":
             error_tolerance = 0.25
         else:
             self.assertTrue(False) # other techs fail
+            
         # Check if no too many or too few results
         self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
 
diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py
index 51fcbca6..84b54e3d 100755
--- a/compiler/tests/23_lib_sram_model_corners_test.py
+++ b/compiler/tests/23_lib_sram_model_corners_test.py
@@ -14,7 +14,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 23_lib_sram_model_corners_test")
+#@unittest.skip("SKIPPING 23_lib_sram_model_corners_test")
 class lib_model_corners_lib_test(openram_test):
 
     def runTest(self):
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index fd75dc25..9fdda7e7 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -14,7 +14,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 23_lib_sram_model_test")
+#@unittest.skip("SKIPPING 23_lib_sram_model_test")
 class lib_sram_model_test(openram_test):
 
     def runTest(self):
diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py
index 2be14001..db75fe0a 100755
--- a/compiler/tests/30_openram_front_end_test.py
+++ b/compiler/tests/30_openram_front_end_test.py
@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 import getpass
 
-@unittest.skip("SKIPPING 30_openram_front_end_test")
+#@unittest.skip("SKIPPING 30_openram_front_end_test")
 class openram_front_end_test(openram_test):
 
     def runTest(self):