From 1b89533d7b23dedcb0b7a60e6a2b51a09028b7fa Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Sun, 1 Aug 2021 00:23:59 -0700 Subject: [PATCH] Added unit r and c values with m2 minwidth incorporated to match CACTI params --- compiler/base/wire_spice_model.py | 3 ++- technology/freepdk45/tech/tech.py | 5 +++-- technology/scn4m_subm/tech/tech.py | 8 ++++---- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/compiler/base/wire_spice_model.py b/compiler/base/wire_spice_model.py index 37efedb5..5e84b64b 100644 --- a/compiler/base/wire_spice_model.py +++ b/compiler/base/wire_spice_model.py @@ -17,7 +17,8 @@ class wire_spice_model(): def cal_wire_c(self, wire_length, wire_width): from tech import spice - total_c = spice["wire_unit_c"] * wire_length * wire_width + # Convert the F/um^2 to fF/um^2 then multiple by width and length + total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width wire_c = total_c / self.lump_num return wire_c diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index cf75ff54..ffc06296 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -425,7 +425,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) # analytical delay parameters spice["nom_threshold"] = 0.4 # Typical Threshold voltage in Volts spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square -spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 +spice["wire_unit_c"] = 0.64e-12 # Unit wire capacitance F/um^2 spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff spice["dff_setup"] = 9 # DFF setup time in ps @@ -468,7 +468,8 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["c_junc"] = 5e-16 #F/um^2 spice["c_junc_sw"] = 5e-16 #F/um -spice["wire_c_per_um"] = 0 # Temp value +spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units +spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units ################################################### # Technology Tool Preferences diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 29ed1332..00ebdf2b 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -370,9 +370,8 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius) # analytical delay parameters spice["nom_threshold"] = 1.3 # Nominal Threshold voltage in Volts -# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45. -spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square -spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 +spice["wire_unit_r"] = 0.07 # Unit wire resistance in ohms/square +spice["wire_unit_c"] = 1.7e-17 # Unit wire capacitance F/um^2 spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff spice["dff_setup"] = 9 # DFF setup time in ps @@ -415,7 +414,8 @@ spice["c_fringe"] = 0 # F/um, not defined in this technology spice["cpolywire"] = 0 # F/um, replicated from CACTI which is hardcoded to 0 spice["c_junc"] = 9.276962e-16 #F/um^2 spice["c_junc_sw"] = 3.181055e-16 #F/um -spice["wire_c_per_um"] = 0 # Temp value +spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units +spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units ################################################### # Technology Tool Preferences