From 2e23fffaddaaf9f304da35fc66c6772b836ed6cd Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 14:18:55 -0700 Subject: [PATCH 1/4] Fix comment --- compiler/verify/magic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 454dc176..18ba53fc 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -74,7 +74,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa magic_file = os.environ.get('OPENRAM_MAGICRC', None) if not magic_file: magic_file = OPTS.openram_tech + "tech/.magicrc" - + if os.path.exists(magic_file): shutil.copy(magic_file, output_path + "/.magicrc") else: @@ -251,7 +251,7 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - # Copy .magicrc file into the output directory + # Copy setup.tcl file into the output directory setup_file = os.environ.get('OPENRAM_NETGENRC', None) if not setup_file: setup_file = OPTS.openram_tech + "tech/setup.tcl" From d6a72aed37dd7f879556b2d3367beeefac709756 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:00:46 -0700 Subject: [PATCH 2/4] Add 2x1 perimter pins to satisfy minimum area rule. --- compiler/router/router.py | 42 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index d5bd4738..f82a6128 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -711,6 +711,27 @@ class router(router_tech): p = pin_layout("", [ll, ur], self.get_layer(track[2])) return p + def convert_tracks_to_pin(self, tracks): + """ + Convert a list of grid point into a rectangle shape. + Must all be on the same layer. + """ + for t in tracks: + debug.check(t[2] == tracks[0][2], "Different layers used.") + + # For each shape, convert it to a pin + pins = [self.convert_track_to_pin(t) for t in tracks] + # Now find the bounding box + minx = min([p.lx() for p in pins]) + maxx = max([p.rx() for p in pins]) + miny = min([p.by() for p in pins]) + maxy = max([p.uy() for p in pins]) + ll = vector(minx, miny) + ur = vector(maxx, maxy) + + p = pin_layout("", [ll, ur], self.get_layer(tracks[0][2])) + return p + def convert_track_to_shape_pin(self, track): """ Convert a grid point into a rectangle shape @@ -1294,10 +1315,27 @@ class router(router_tech): def get_perimeter_pin(self): """ Return the shape of the last routed path that was on the perimeter """ - for v in self.paths[-1]: + lastpath = self.paths[-1] + for v in lastpath: if self.rg.is_target(v): + # Find neighboring grid to make double wide pin + neighbor = v + vector3d(0, 1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(0, -1, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + neighbor = v + vector3d(-1, 0, 0) + if neighbor in lastpath: + return self.convert_tracks_to_pin([v, neighbor]) + + # Else if we came from a different layer, we can only add + # a signle grid return self.convert_track_to_pin(v) - + return None def get_ll_pin(self, pin_name): From 53107a8322b5ba48081ef66de62b7eec752c95ea Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:03:41 -0700 Subject: [PATCH 3/4] Add ring test --- compiler/tests/20_sram_1bank_ring_test.py | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100755 compiler/tests/20_sram_1bank_ring_test.py diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py new file mode 100755 index 00000000..e34920c2 --- /dev/null +++ b/compiler/tests/20_sram_1bank_ring_test.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2021 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +class sram_1bank_nomux_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + OPTS.supply_pin_type = "ring" + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + + c.words_per_row=1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 159d0ed603e07201390efeaeeb9f1ade89bfc261 Mon Sep 17 00:00:00 2001 From: mrg Date: Sun, 13 Jun 2021 15:08:05 -0700 Subject: [PATCH 4/4] Fix s_en spacing problem. --- compiler/sram/sram_1bank.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 828edfdd..030b0c33 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -452,7 +452,6 @@ class sram_1bank(sram_base): y_bottom = 0 y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch - offset = vector(self.control_logic_insts[port].rx() + self.dff.width, y_offset) cr = channel_route(netlist=route_map,