From 1a72070f042ede8755387b874455aa7ed10a3d0f Mon Sep 17 00:00:00 2001 From: jsowash Date: Tue, 3 Sep 2019 17:14:31 -0700 Subject: [PATCH] Removed LVS error where w_en went over whole AND array in 2 port. --- compiler/modules/bank.py | 5 ++++- compiler/modules/write_mask_and_array.py | 5 +++-- compiler/tests/10_write_mask_and_array_test.py | 10 +++++----- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 0ae53b31..3e105d09 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -930,7 +930,10 @@ class bank(design.design): connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) if port in self.write_ports: - connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) + if port % 2: + connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").rc())) + else: + connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) if port in self.read_ports: connection.append((self.prefix+"s_en{}".format(port), self.port_data_inst[port].get_pin("s_en").lc())) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index 69f1a4fd..0ba717cd 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -20,7 +20,7 @@ class write_mask_and_array(design.design): The write mask AND array goes between the write driver array and the sense amp array. """ - def __init__(self, name, columns, word_size, write_size, port): + def __init__(self, name, columns, word_size, write_size, port=0): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) @@ -122,10 +122,11 @@ class write_mask_and_array(design.design): layer="metal3", offset=beg_en_pin.bc(), width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge) + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) self.add_via_center(layers=("metal2", "via2", "metal3"), offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy())) - for i in range(self.num_wmasks): # Copy remaining layout pins self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i)) diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py index 6334ac97..91155467 100755 --- a/compiler/tests/10_write_mask_and_array_test.py +++ b/compiler/tests/10_write_mask_and_array_test.py @@ -24,15 +24,15 @@ class write_mask_and_array_test(openram_test): # check write driver array for single port debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4") - a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4, port=0) + a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) self.local_check(a) debug.info(2, "Testing write_mask_and_array for columns=16, word_size=16, write_size=4") - a = factory.create(module_type="write_mask_and_array", columns=16, word_size=16, write_size=4, port=0) + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=16, write_size=4) self.local_check(a) debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2") - a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2, port=0) + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) # check write driver array for multi-port @@ -43,11 +43,11 @@ class write_mask_and_array_test(openram_test): factory.reset() debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)") - a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4, port=0) + a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4) self.local_check(a) debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)") - a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2, port=0) + a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2) self.local_check(a) globals.end_openram()