diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 855711c5..69eee383 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -43,7 +43,7 @@ class timing_sram_test(openram_test): probe_data = s.word_size - 1 debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) - d = delay.delay(s,tempspice,tech.spice["nom_delay"]) + d = delay.delay(s,tempspice,tech.spice["nom_corner"]) import tech loads = [tech.spice["msflop_in_cap"]*4] slews = [tech.spice["rise_time"]*2] diff --git a/compiler/tests/22_sram_func_test.py b/compiler/tests/22_sram_func_test.py index ec6eabf2..bbbc334b 100644 --- a/compiler/tests/22_sram_func_test.py +++ b/compiler/tests/22_sram_func_test.py @@ -43,7 +43,7 @@ class sram_func_test(openram_test): probe_data = s.word_size - 1 debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data)) - d = delay.delay(s,tempspice) + d = delay.delay(s,tempspice,tech.spice["nom_corner"]) d.set_probe(probe_address,probe_data) # This will exit if it doesn't find a feasible period diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 69288350..b7a200dc 100644 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -52,11 +52,16 @@ class openram_test(openram_test): os.system(cmd) # assert an error until we actually check a resul - for extension in ["gds", "v", "lef", "lib", "sp"]: + for extension in ["gds", "v", "lef", "sp"]: filename = "{0}/{1}.{2}".format(out_path,out_file,extension) debug.info(1,"Checking for file: " + filename) self.assertEqual(os.path.exists(filename),True) + # Make sure there is any .lib file + import glob + files = glob.glob('{0}/*.lib'.format(out_path)) + self.assertTrue(len(files)>0) + # grep any errors from the output output = open("{0}/output.log".format(out_path),"r").read() self.assertEqual(len(re.findall('ERROR',output)),0)