diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 48da3630..1abd5553 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -101,15 +101,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.replica_columns = {} for bit in range(self.add_left_rbl + self.add_right_rbl): # Creating left_rbl - if bit