diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 3b80f056..9774739d 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -813,7 +813,7 @@ class delay(simulation):
 
             result[port].update(read_port_dict)
             
-            self.check_path_measures()
+            self.path_delays = self.check_path_measures()
 
         return (True, result)
 
@@ -927,7 +927,7 @@ class delay(simulation):
             if type(val) != float or val > self.period/2:
                 debug.info(1,'Failed measurement:{}={}'.format(meas.name, val))
             value_dict[meas.name] = val
-        
+        #debug.info(0, "value_dict={}".format(value_dict))
         return value_dict
 
     def run_power_simulation(self):
@@ -1153,10 +1153,17 @@ class delay(simulation):
         # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
         self.period = min_period
         char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
-
+        if len(load_slews) > 1:
+            debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
+        # Get and save the path delays
+        bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
+        char_sram_data["bl_path_delays"] = bl_delays
+        char_sram_data["sen_path_delays"] = sen_delays
+        char_sram_data["bl_path_names"] = bl_names
+        char_sram_data["sen_path_names"] = sen_names
         # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate.
         self.alter_lh_char_data(char_port_data)
-
+           
         return (char_sram_data, char_port_data)
 
     def alter_lh_char_data(self, char_port_data):
@@ -1171,6 +1178,7 @@ class delay(simulation):
         """Simulate all specified output loads and input slews pairs of all ports"""
 
         measure_data = self.get_empty_measure_data_dict()
+        path_dict = {}
         # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
         self.targ_read_ports = self.read_ports
         self.targ_write_ports = self.write_ports
@@ -1190,6 +1198,22 @@ class delay(simulation):
                         measure_data[port][mname].append(value)
         return measure_data
 
+    def get_delay_lists(self, value_dict):
+        """Returns dicts for path measures of bitline and sen paths"""
+        sen_name_list = []
+        sen_delay_list = []
+        for meas in self.sen_path_meas:
+            sen_name_list.append(meas.name)
+            sen_delay_list.append(value_dict[meas.name])
+        
+        bl_name_list = []
+        bl_delay_list = []
+        for meas in self.bl_path_meas:
+            bl_name_list.append(meas.name)
+            bl_delay_list.append(value_dict[meas.name])
+
+        return sen_name_list, sen_delay_list, bl_name_list, bl_delay_list 
+
     def calculate_inverse_address(self):
         """Determine dummy test address based on probe address and column mux size."""
 
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 0d69bba3..1525924d 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -638,10 +638,21 @@ class lib:
                 probe_address = "0" + "1" * (self.sram.addr_size - 1)
             probe_data = self.sram.word_size - 1
             char_results = self.d.analyze(probe_address, probe_data, self.load_slews)
+            
+            
+            
         self.char_sram_results, self.char_port_results = char_results
         if 'sim_time' in self.char_sram_results:
             self.pred_time = self.char_sram_results['sim_time']
-        
+        # Add to the OPTS to be written out as part of the extended OPTS file
+        # FIXME: should be written to datasheet, current version is simplifies current use of this    
+        if not self.use_model:
+            OPTS.sen_path_delays = self.char_sram_results["sen_path_delays"]
+            OPTS.sen_path_names = self.char_sram_results["sen_path_names"]
+            OPTS.bl_path_delays = self.char_sram_results["bl_path_delays"]
+            OPTS.bl_path_names = self.char_sram_results["bl_path_names"]
+  
+            
     def compute_setup_hold(self):
         """ Do the analysis if we haven't characterized a FF yet """
         # Do the analysis if we haven't characterized a FF yet
@@ -866,3 +877,5 @@ class lib:
             datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power))
         
         
+ 
+