diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index f02a4f0e..317ebe8f 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -72,7 +72,7 @@ class bank(design.design):
         # self.add_lvs_correspondence_points()
 
         # Remember the bank center for further placement
-        #self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)
+        self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)
         self.bank_array_ur = self.bitcell_array_inst.ur()
         self.bank_array_ul = self.bitcell_array_inst.ul()
         self.DRC_LVS()
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index 6bc2cd43..cf4c08e8 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -140,6 +140,7 @@ class sram_1bank(sram_base):
         # This includes 2 M2 pitches for the row addr clock line.
         # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
         # using the control_logic_center value.
+        breakpoint()
         self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
                                         self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
         self.control_logic_insts[port].place(self.control_pos[port])