diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 2823a415..62367d72 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -59,7 +59,8 @@ class delay(simulation): """ Create measurement names. The names themselves currently define the type of measurement """ self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"] - self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power", "disabled_read0_power", "disabled_read1_power"] + self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power", + "disabled_read0_power", "disabled_read1_power", "disabled_write0_power", "disabled_write1_power"] # self.voltage_when_names = ["volt_bl", "volt_br"] # self.bitline_delay_names = ["delay_bl", "delay_br"] @@ -161,6 +162,11 @@ class delay(simulation): self.write_lib_meas.append(power_measure("write0_power", "FALL", measure_scale=1e3)) self.write_lib_meas[-1].meta_str = sram_op.WRITE_ZERO + self.write_lib_meas.append(power_measure("disabled_write1_power", "RISE", measure_scale=1e3)) + self.write_lib_meas[-1].meta_str = "disabled_write1" + self.write_lib_meas.append(power_measure("disabled_write0_power", "FALL", measure_scale=1e3)) + self.write_lib_meas[-1].meta_str = "disabled_write0" + write_measures = [] write_measures.append(self.write_lib_meas) write_measures.append(self.create_write_bit_measures()) @@ -1203,6 +1209,9 @@ class delay(simulation): write_port) self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times)-1 + self.add_noop_clock_one_port(write_port) + self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times)-1 + # This also ensures we will have a H->L transition on the next read self.add_read("R data 1 address {} to set dout caps".format(inverse_address), inverse_address, @@ -1213,8 +1222,9 @@ class delay(simulation): read_port) self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1 - self.add_nop(self.probe_address, data_zeros, read_port) - self.measure_cycles[write_port]["disabled_read0"] = len(self.cycle_times) - 1 + self.add_noop_clock_one_port(read_port) + self.measure_cycles[read_port]["disabled_read0"] = len(self.cycle_times) - 1 + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)") @@ -1225,14 +1235,18 @@ class delay(simulation): write_port) self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times)-1 + self.add_noop_clock_one_port(write_port) + self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times)-1 + self.add_write("W data 0 address {} to clear din caps".format(inverse_address), inverse_address, data_zeros, wmask_ones, write_port) - self.add_nop(self.probe_address, data_zeros, read_port) - self.measure_cycles[write_port]["disabled_read1"] = len(self.cycle_times) - 1 + self.add_noop_clock_one_port(read_port) + self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1 + # This also ensures we will have a L->H transition on the next read self.add_read("R data 0 address {} to clear dout caps".format(inverse_address), diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9f3c12d3..57e21763 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -534,6 +534,19 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") + # Disabled power. + disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) + disabled_read0_power = np.mean(self.char_port_results[port]["disabled_raed0_power"]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) + self.lib.write(" }\n") + self.lib.write(" }\n") + if port in self.read_ports: if port in self.write_ports: web_name = " & web{0}".format(port) @@ -549,18 +562,18 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") - # Disabled power. - disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"]) - disabled_read0_power = np.mean(self.char_port_results[port]["disabled_read0_power"]) - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"csb{0}\"; \n".format(port)) - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power)) - self.lib.write(" }\n") - self.lib.write(" }\n") + # Disabled power. + disabled_write1_power = np.mean(self.char_port_results[port]["disabled_write1_power"]) + disabled_write0_power = np.mean(self.char_port_results[port]["disabled_write0_power"]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write1_power)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write0_power)) + self.lib.write(" }\n") + self.lib.write(" }\n") def write_pg_pin(self): self.lib.write(" pg_pin(vdd) {\n") diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 0cfc860f..0d5cfb25 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -210,22 +210,6 @@ class simulation(): if unselected_port != port: self.add_noop_one_port(unselected_port) - def add_nop(self, address, din_data, port): - """ Add the control values for a cycle with clock only. Does not increment the period. """ - debug.check(port in self.read_ports or port in self.write_ports, - "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports)) - debug.info(2, 'Clock only on port {}'.format(port)) - self.fn_cycle_comments.append('Clock only on port {}'.format(port)) - self.append_cycle_comment(port, 'Clock only on port {}'.format(port)) - - self.cycle_times.append(self.t_current) - self.t_current += self.period - self.add_control_one_port(port, "noop") - # If the port is also a readwrite then add data. - if port in self.write_ports: - self.add_data(din_data, port) - self.add_address(address, port) - def add_noop_all_ports(self, comment): """ Add the control values for a noop to all ports. """ debug.info(2, comment) @@ -295,6 +279,23 @@ class simulation(): except: self.add_wmask("0"*self.num_wmasks, port) + def add_noop_clock_one_port(self, port): + """ Add the control values for a noop to a single port. Increments the period. """ + debug.info(2, 'Clock only on port {}'.format(port)) + self.fn_cycle_comments.append('Clock only on port {}'.format(port)) + self.append_cycle_comment(port, 'Clock only on port {}'.format(port)) + + self.cycle_times.append(self.t_current) + self.t_current += self.period + + self.add_noop_one_port(port) + + #Add noops to all other ports. + for unselected_port in self.all_ports: + if unselected_port != port: + self.add_noop_one_port(unselected_port) + + def append_cycle_comment(self, port, comment): """Add comment to list to be printed in stimulus file""" #Clean up time before appending. Make spacing dynamic as well.