From 119bcb9197a51641580f947b225b3f54daa8c437 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 14 Dec 2022 08:12:55 -0800 Subject: [PATCH] route unused wordlines (still failing lvs) --- compiler/modules/capped_bitcell_array.py | 10 ++++++---- compiler/modules/replica_bitcell_array.py | 7 ++----- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/compiler/modules/capped_bitcell_array.py b/compiler/modules/capped_bitcell_array.py index f04eb60f..1c9d2d51 100644 --- a/compiler/modules/capped_bitcell_array.py +++ b/compiler/modules/capped_bitcell_array.py @@ -226,7 +226,7 @@ class capped_bitcell_array(bitcell_base_array): # Array was at (0, 0) but move everything so it is at the lower left # We move DOWN the number of left RBL even if we didn't add the column to this bitcell array # Note that this doesn't include the row/col cap - array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0]) + array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0]) self.translate_all(array_offset.scale(-1, -1)) # Add extra width on the left and right for the unused WLs @@ -302,8 +302,10 @@ class capped_bitcell_array(bitcell_base_array): self.dummy_col_insts[1].place(offset=dummy_col_offset) def copy_layout_pins(self): - for pin_name in self.replica_bitcell_array_inst.get_pins(): - if pin_name in ["vdd", "gnd"]: + excluded_pins = ["vdd", "gnd"] + excluded_pins.extend(self.unused_wordline_names) + for pin_name in self.replica_bitcell_array.get_pin_names(): + if pin_name in excluded_pins: continue self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name) @@ -375,7 +377,7 @@ class capped_bitcell_array(bitcell_base_array): # Ground the unused replica wordlines for (names, inst) in zip(self.replica_bitcell_array.rbl_wordline_names, self.replica_bitcell_array.dummy_row_replica_insts): for (wl_name, pin_name) in zip(names, self.replica_bitcell_array.dummy_row.get_wordline_names()): - if wl_name in self.replica_bitcell_array.unused_wordline_names: + if wl_name in self.unused_wordline_names: pin = inst.get_pin(pin_name) self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x) self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index fb0c2935..07cbc405 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -225,7 +225,7 @@ class replica_bitcell_array(bitcell_base_array): # Dummy rows above/below the bitcell array (connected with the replica cell wl) self.dummy_row_replica_insts = [] # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! - for port in self.all_ports: + for port in self.all_ports: # TODO: tie to self.rbl or whatever self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), mod=self.dummy_row)) self.connect_inst(self.all_bitcell_bitline_names + self.rbl_wordline_names[port] + self.supplies) @@ -253,15 +253,12 @@ class replica_bitcell_array(bitcell_base_array): array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0]) self.translate_all(array_offset.scale(-1, -1)) - self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x - self.height = self.dummy_row_insts[1].uy() - self.add_layout_pins() self.route_supplies() - self.width = (len(self.rbls) + self.column_size) * self.cell.width self.height = (len(self.rbls) + self.row_size) * self.cell.height + self.width = (len(self.rbls) + self.column_size) * self.cell.width self.add_boundary()