From 10ced3312742b64c698b68373acc64a73624bcc4 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sun, 21 Jan 2018 11:21:09 -0800 Subject: [PATCH] Fixed command line arguments to take priority over config file. Any option can be specified in config file now. --- compiler/globals.py | 10 +++--- compiler/tests/30_openram_test.py | 9 +++-- compiler/tests/config_20_freepdk45.py | 3 -- compiler/tests/config_20_scn3me_subm.py | 4 --- docs/intro.tex | 18 ++++++---- docs/openram_manual.out | 47 ------------------------- 6 files changed, 23 insertions(+), 68 deletions(-) delete mode 100644 docs/openram_manual.out diff --git a/compiler/globals.py b/compiler/globals.py index 0ce86d11..b0a81be5 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -60,7 +60,6 @@ def parse_args(): version="OpenRAM v" + VERSION) (options, args) = parser.parse_args(values=OPTS) - # If we don't specify a tech, assume freepdk45. # This may be overridden when we read a config file though... if OPTS.tech_name == "": @@ -149,10 +148,13 @@ def read_config(config_file): except: debug.error("Unable to read configuration file: {0}".format(config_file),2) - # The config file will over-ride all command line args for k,v in config.__dict__.items(): - OPTS.__dict__[k]=v - + # The command line will over-ride the config file + # except in the case of the tech name! This is because the tech name + # is sometimes used to specify the config file itself (e.g. unit tests) + if not k in OPTS.__dict__ or k=="tech_name": + OPTS.__dict__[k]=v + if not OPTS.output_path.endswith('/'): OPTS.output_path += "/" debug.info(1, "Output saved in " + OPTS.output_path) diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index c756d3fc..f0ad17f4 100644 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -17,11 +17,11 @@ class openram_test(unittest.TestCase): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - + debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" # make a temp directory for output - out_path = OPTS.openram_temp + out_file + out_path = "/tmp/testsram" # make sure we start without the files existing if os.path.exists(out_path): @@ -67,7 +67,10 @@ class openram_test(unittest.TestCase): shutil.rmtree(out_path, ignore_errors=True) self.assertEqual(os.path.exists(out_path),False) - globals.end_openram() + # The default was on, so disable it. + OPTS.check_lvsdrc=False + globals.end_openram() + OPTS.check_lvsdrc=True # instantiate a copy of the class to actually run the test if __name__ == "__main__": diff --git a/compiler/tests/config_20_freepdk45.py b/compiler/tests/config_20_freepdk45.py index 14f9218b..4eb4f091 100644 --- a/compiler/tests/config_20_freepdk45.py +++ b/compiler/tests/config_20_freepdk45.py @@ -4,7 +4,4 @@ num_banks = 1 tech_name = "freepdk45" -# Optional, will be over-ridden on command line. -output_path = "/tmp/freepdk45_sram" -output_name = "sram_2_16_1_freepdk45" diff --git a/compiler/tests/config_20_scn3me_subm.py b/compiler/tests/config_20_scn3me_subm.py index b155943a..178eb91e 100644 --- a/compiler/tests/config_20_scn3me_subm.py +++ b/compiler/tests/config_20_scn3me_subm.py @@ -4,7 +4,3 @@ num_banks = 1 tech_name = "scn3me_subm" -# Optional, will be over-ridden on command line. -output_path = "/tmp/scn3me_subm_mysram" -output_name = "sram_2_16_1_scn3me_subm" - diff --git a/docs/intro.tex b/docs/intro.tex index 73b0afcb..5da2f731 100644 --- a/docs/intro.tex +++ b/docs/intro.tex @@ -218,14 +218,18 @@ also includes parameters for the output path, base output file name, and technology of an SRAM. The configuration file can be used to over-ride any option in the -options.py file. Many of these are controlled by the command-line, -but the configuration file takes priority and allows repeatable -generation of memories. +options.py file. Many of these can also be controlled by the command-line +which over-ride the configuration file. -Lastly, the configuration file can over-ride any -of the different circuit implementations for each module. For example, you -can replace the default address decoder or bitcell with a new one by -specifying a new python module that implements a new one. +The one exception is the technology name. The technology name of a +config file will over-ride a command-line option. The unit tests use +the command line to read a configuration file, so it is a chicken and +egg situation. + +Lastly, the configuration file can over-ride any of the different +circuit implementations for each module. For example, you can replace +the default address decoder or bitcell with a new one by specifying a +new python module that implements a new one. An entire example configuration file looks like: \begin{verbatim} diff --git a/docs/openram_manual.out b/docs/openram_manual.out deleted file mode 100644 index 404fe9f1..00000000 --- a/docs/openram_manual.out +++ /dev/null @@ -1,47 +0,0 @@ -\BOOKMARK [1][-]{section.1}{License}{}% 1 -\BOOKMARK [1][-]{section.2}{Introduction}{}% 2 -\BOOKMARK [2][-]{subsection.2.1}{Requirements}{section.2}% 3 -\BOOKMARK [2][-]{subsection.2.2}{Environment Variables}{section.2}% 4 -\BOOKMARK [2][-]{subsection.2.3}{Design Flow}{section.2}% 5 -\BOOKMARK [2][-]{subsection.2.4}{Usage}{section.2}% 6 -\BOOKMARK [1][-]{section.3}{Overview of the SRAM Structure}{}% 7 -\BOOKMARK [2][-]{subsection.3.1}{Inputs/Outputs}{section.3}% 8 -\BOOKMARK [2][-]{subsection.3.2}{Top-Level SRAM Module}{section.3}% 9 -\BOOKMARK [1][-]{section.4}{Modules}{}% 10 -\BOOKMARK [2][-]{subsection.4.1}{The Bitcell and Bitcell Array}{section.4}% 11 -\BOOKMARK [2][-]{subsection.4.2}{Precharge Circuitry}{section.4}% 12 -\BOOKMARK [2][-]{subsection.4.3}{Address Decoders}{section.4}% 13 -\BOOKMARK [2][-]{subsection.4.4}{Wordline Driver}{section.4}% 14 -\BOOKMARK [2][-]{subsection.4.5}{Column Mux}{section.4}% 15 -\BOOKMARK [2][-]{subsection.4.6}{Sense Amplifier}{section.4}% 16 -\BOOKMARK [2][-]{subsection.4.7}{Write Driver}{section.4}% 17 -\BOOKMARK [2][-]{subsection.4.8}{Flip-Flop Array}{section.4}% 18 -\BOOKMARK [2][-]{subsection.4.9}{Control Logic}{section.4}% 19 -\BOOKMARK [1][-]{section.5}{Bank and SRAM}{}% 20 -\BOOKMARK [1][-]{section.6}{Software Implementation}{}% 21 -\BOOKMARK [2][-]{subsection.6.1}{Design Hierarchy}{section.6}% 22 -\BOOKMARK [2][-]{subsection.6.2}{Creating a New Design Module}{section.6}% 23 -\BOOKMARK [2][-]{subsection.6.3}{GDSII Files and GdsMill\)}{section.6}% 24 -\BOOKMARK [2][-]{subsection.6.4}{Technology Directory}{section.6}% 25 -\BOOKMARK [2][-]{subsection.6.5}{DRC/LVS Interface}{section.6}% 26 -\BOOKMARK [1][-]{section.7}{Custom Layout Design Functions in Software}{}% 27 -\BOOKMARK [2][-]{subsection.7.1}{Parameterized Transistor}{section.7}% 28 -\BOOKMARK [2][-]{subsection.7.2}{Parameterized Inverter}{section.7}% 29 -\BOOKMARK [2][-]{subsection.7.3}{Parameterized NAND2}{section.7}% 30 -\BOOKMARK [2][-]{subsection.7.4}{Parameterized NAND3}{section.7}% 31 -\BOOKMARK [2][-]{subsection.7.5}{Parameterized NOR2}{section.7}% 32 -\BOOKMARK [2][-]{subsection.7.6}{Path and Wire}{section.7}% 33 -\BOOKMARK [1][-]{section.8}{Porting to a new Technologies}{}% 34 -\BOOKMARK [2][-]{subsection.8.1}{The GDS and Spice Libraries}{section.8}% 35 -\BOOKMARK [2][-]{subsection.8.2}{Technology Directory}{section.8}% 36 -\BOOKMARK [1][-]{section.9}{Timing and Control Logic}{}% 37 -\BOOKMARK [2][-]{subsection.9.1}{Signals}{section.9}% 38 -\BOOKMARK [2][-]{subsection.9.2}{Timing Considerations}{section.9}% 39 -\BOOKMARK [2][-]{subsection.9.3}{SRAM Operation}{section.9}% 40 -\BOOKMARK [2][-]{subsection.9.4}{Zero Bus Turnaround \(ZBT\)}{section.9}% 41 -\BOOKMARK [2][-]{subsection.9.5}{Control Logic}{section.9}% 42 -\BOOKMARK [2][-]{subsection.9.6}{Replica Bitline Delay}{section.9}% 43 -\BOOKMARK [2][-]{subsection.9.7}{Timing and Power Characterizer}{section.9}% 44 -\BOOKMARK [1][-]{section.10}{Unit Tests}{}% 45 -\BOOKMARK [2][-]{subsection.10.1}{Usage}{section.10}% 46 -\BOOKMARK [1][-]{section.11}{Debug Framework}{}% 47