From 0f9e38881c5736e732df1c8ea83db0b0cd4beaa2 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Mon, 4 May 2020 03:05:33 -0700 Subject: [PATCH] update stim for large pex layouts --- compiler/characterizer/stimuli.py | 6 +++--- compiler/sram/sram_base.py | 6 +++--- compiler/verify/magic.py | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5e0bd52e..c8ee0492 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -58,11 +58,11 @@ class stimuli(): for pin in pins: self.sf.write("{0} ".format(pin)) for bank in range(OPTS.num_banks): - for row in range(OPTS.num_words): - for col in range(OPTS.word_size): + for row in range(int(OPTS.num_words / OPTS.words_per_row)): + for col in range(int(OPTS.word_size * OPTS.words_per_row)): self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)) self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)) - for col in range(OPTS.word_size): + for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): self.sf.write("bl{0}_{2} ".format(port, row, col)) self.sf.write("br{0}_{2} ".format(port, row, col)) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 652615dd..3cace3d6 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -114,9 +114,9 @@ class sram_base(design, verilog, lef): for cell in range(len(bank_offset)): Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] - - self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))) , storage_layer_name, Q) - self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))), storage_layer_name, Q_bar) + OPTS.words_per_row = self.words_per_row + self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))) , storage_layer_name, Q) + self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.word_size * self.words_per_row))), storage_layer_name, Q_bar) for cell in range(len(bl_offsets)): col = bl_meta[cell][0][2] diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 432325ea..de206b87 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -415,11 +415,11 @@ def correct_port(name, output_file_name, ref_file_name): bitcell_list = "+ " for bank in range(OPTS.num_banks): - for row in range(OPTS.num_words): - for col in range(OPTS.word_size): + for row in range(int(OPTS.num_words / OPTS.words_per_row)): + for col in range(int(OPTS.word_size * OPTS.words_per_row)): bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col) bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col) - for col in range(OPTS.word_size): + for col in range(OPTS.word_size * OPTS.words_per_row): for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports): bitcell_list += "bl{0}_{2} ".format(bank, row, col) bitcell_list += "br{0}_{2} ".format(bank, row, col)