diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 4d4ad76b..24dc1c03 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 9e221f07..9de8fb77 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") class psram_1bank_2mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 5facb482..f88f1364 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -49,29 +49,28 @@ class timing_sram_test(openram_test): #Combine info about port into all data data.update(port_data[0]) - #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], - 'leakage_power': 0.0019498999999999996, + golden_data = {'delay_hl': [2.6232], + 'delay_lh': [0.2775342], + 'leakage_power': 0.0020258999999999997, 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} + 'read0_power': [0.0557804], + 'read1_power': [0.0525619], + 'slew_hl': [0.1082014], + 'slew_lh': [0.0238257], + 'write0_power': [0.0456528], + 'write1_power': [0.0442747]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.452], - 'delay_lh': [1.3792000000000002], - 'leakage_power': 0.0257065, - 'min_period': 4.688, - 'read0_power': [15.0755], - 'read1_power': [14.4526], - 'slew_hl': [0.6137363], - 'slew_lh': [0.3381045], - 'write0_power': [16.9203], - 'write1_power': [15.367]} + golden_data = {'delay_hl': [6.079300000000001], + 'delay_lh': [1.7767000000000002], + 'leakage_power': 0.026282499999999997, + 'min_period': 9.375, + 'read0_power': [6.5802], + 'read1_power': [6.2815], + 'slew_hl': [0.7396921999999999], + 'slew_lh': [0.3397355], + 'write0_power': [5.7337], + 'write1_power': [5.8691]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index e203b878..47c72e78 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], - 'leakage_power': 0.0009567935, + golden_data = {'delay_hl': [2.625351], + 'delay_lh': [0.28080869999999997], + 'leakage_power': 0.001040682, 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} + 'read0_power': [0.0553667], + 'read1_power': [0.05177618], + 'slew_hl': [0.1099853], + 'slew_lh': [0.02568626], + 'write0_power': [0.04517803], + 'write1_power': [0.04449207]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.644147], - 'delay_lh': [1.629815], - 'leakage_power': 0.001542964, - 'min_period': 4.688, - 'read0_power': [16.28732], - 'read1_power': [15.75155], - 'slew_hl': [0.6722473], - 'slew_lh': [0.3386347], - 'write0_power': [18.545450000000002], - 'write1_power': [16.81084]} + golden_data = {'delay_hl': [6.45408], + 'delay_lh': [2.0787519999999997], + 'leakage_power': 0.001177846, + 'min_period': 9.688, + 'read0_power': [7.088419], + 'read1_power': [6.824107000000001], + 'slew_hl': [0.7980976999999999], + 'slew_lh': [0.3393389], + 'write0_power': [5.982207], + 'write1_power': [6.28866]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index a8d6dab2..49b549ed 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -35,10 +35,13 @@ class psram_1bank_4mux_func_test(openram_test): num_words=256, num_banks=1) c.words_per_row=4 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 1a0a1ec5..af5e6abc 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -35,10 +35,13 @@ class psram_1bank_8mux_func_test(openram_test): num_words=256, num_banks=1) c.words_per_row=8 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice)