From 0c9f52e22f3b8a9d1107cf1ebce746ac2f17b28a Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Sun, 28 Jun 2020 07:15:06 -0700
Subject: [PATCH] Realign col decoder and control by 1/4 so metal can pass over

---
 compiler/modules/bank.py    | 11 ++++++++---
 compiler/sram/sram_1bank.py | 13 +++++++++----
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 6134b143..7bbed020 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -217,11 +217,12 @@ class bank(design.design):
         # Place the col decoder left aligned with wordline driver
         # This is also placed so that it's supply rails do not align with the SRAM-level
         # control logic to allow control signals to easily pass over in M3
-        # by placing 1/2 a cell pitch down
+        # by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs
+        # may be routed in M3 or M4
         x_offset = self.central_bus_width[port] + self.port_address.wordline_driver.width
         if self.col_addr_size > 0:
             x_offset += self.column_decoder.width + self.col_addr_bus_width
-            y_offset = 0.5 * self.dff.height + self.column_decoder.height
+            y_offset = 1.25 * self.dff.height + self.column_decoder.height
         else:
             y_offset = 0
         self.column_decoder_offsets[port] = vector(-x_offset, -y_offset)
@@ -258,10 +259,14 @@ class bank(design.design):
         # UPPER RIGHT QUADRANT
         # Place the col decoder right aligned with wordline driver
         # Above the bitcell array with a well spacing
+        # This is also placed so that it's supply rails do not align with the SRAM-level
+        # control logic to allow control signals to easily pass over in M3
+        # by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs
+        # may be routed in M3 or M4
         x_offset = self.bitcell_array_right  + self.central_bus_width[port] + self.port_address.wordline_driver.width
         if self.col_addr_size > 0:
             x_offset += self.column_decoder.width + self.col_addr_bus_width
-            y_offset = self.bitcell_array_top + 0.5 * self.dff.height + self.column_decoder.height
+            y_offset = self.bitcell_array_top + 1.25 * self.dff.height + self.column_decoder.height
         else:
             y_offset = self.bitcell_array_top
         self.column_decoder_offsets[port] = vector(x_offset, y_offset)
diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py
index 4e2be40e..b8efd195 100644
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@@ -77,8 +77,10 @@ class sram_1bank(sram_base):
         port = 0
 
         # This includes 2 M2 pitches for the row addr clock line.
+        # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
+        # using the control_logic_center value.
         control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
-                                   self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - 2 * self.bank.m2_gap)
+                                   self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
         self.control_logic_insts[port].place(control_pos[port])
         
         # The row address bits are placed above the control logic aligned on the right.
@@ -129,10 +131,13 @@ class sram_1bank(sram_base):
             port = 1
         
             # This includes 2 M2 pitches for the row addr clock line
+            # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
+            # using the control_logic_center value.
             control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2 * self.m2_pitch,
-                                       self.bank.bank_array_ur.y + self.control_logic_insts[port].height - \
-                                       (self.control_logic_insts[port].height - self.control_logic_insts[port].mod.control_logic_center.y)
-                                       + 2 * self.bank.m2_gap)
+                                       self.bank.bank_array_ur.y
+                                       + self.control_logic_insts[port].height
+                                       - self.control_logic_insts[port].height
+                                       + self.control_logic_insts[port].mod.control_logic_center.y)
             self.control_logic_insts[port].place(control_pos[port], mirror="XY")
         
             # The row address bits are placed above the control logic aligned on the left.