From 0c3baa51728fa7c742c701a7968bab5c2fbeb899 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 25 Jan 2019 15:00:00 -0800 Subject: [PATCH] Added some comments to the spice files. --- compiler/modules/bitcell_array.py | 2 +- compiler/modules/control_logic.py | 3 +++ compiler/modules/delay_chain.py | 4 +++- compiler/modules/dff_array.py | 5 +++-- compiler/modules/dff_buf.py | 3 ++- compiler/modules/dff_buf_array.py | 3 +++ compiler/modules/dff_inv.py | 2 ++ compiler/modules/dff_inv_array.py | 3 +++ compiler/modules/precharge_array.py | 3 ++- compiler/modules/sense_amp_array.py | 2 ++ compiler/modules/single_level_column_mux_array.py | 2 ++ compiler/modules/wordline_driver.py | 4 +++- compiler/modules/write_driver_array.py | 2 ++ compiler/sram_factory.py | 4 ++-- 14 files changed, 33 insertions(+), 9 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 166437fa..67e5a9da 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -14,7 +14,7 @@ class bitcell_array(design.design): def __init__(self, cols, rows, name): design.design.__init__(self, name) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) - + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) self.column_size = cols self.row_size = rows diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 781402de..805cbea9 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -19,6 +19,9 @@ class control_logic(design.design): name = "control_logic_" + port_type design.design.__init__(self, name) debug.info(1, "Creating {}".format(name)) + self.add_comment("num_rows: {0}".format(num_rows)) + self.add_comment("words_per_row: {0}".format(words_per_row)) + self.add_comment("word_size {0}".format(word_size)) self.sram=sram self.num_rows = num_rows diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 848e4e85..f3d15ba3 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -16,7 +16,9 @@ class delay_chain(design.design): def __init__(self, name, fanout_list): """init function""" design.design.__init__(self, name) - + debug.info(1, "creating delay chain {0}".format(str(fanout_list))) + self.add_comment("fanouts: {0}".format(str(fanout_list))) + # Two fanouts are needed so that we can route the vdd/gnd connections for f in fanout_list: debug.check(f>=2,"Must have >=2 fanouts for each stage.") diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 215d2884..5d728205 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -12,7 +12,7 @@ class dff_array(design.design): Unlike the data flops, these are never spaced out. """ - def __init__(self, rows, columns, inv1_size=2, inv2_size=4, name=""): + def __init__(self, rows, columns, name=""): self.rows = rows self.columns = columns @@ -20,7 +20,8 @@ class dff_array(design.design): name = "dff_array_{0}x{1}".format(rows, columns) design.design.__init__(self, name) debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns)) - + self.add_comment("rows: {0} cols: {1}".format(rows, columns)) + self.create_netlist() if not OPTS.netlist_only: self.create_layout() diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 4f6fff11..42d37bd1 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -21,7 +21,8 @@ class dff_buf(design.design): dff_buf.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) - + self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size)) + # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width. # This causes a DRC in the pinv which assumes min width rails. This ensures the output # contact does not violate spacing to the rail in the NMOS. diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 4d655a64..b179b1c3 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -22,6 +22,9 @@ class dff_buf_array(design.design): dff_buf_array.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) + self.add_comment("rows: {0} cols: {1}".format(rows, columns)) + self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size)) + self.inv1_size = inv1_size self.inv2_size = inv2_size diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index f8ff00bf..436026bb 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -20,6 +20,8 @@ class dff_inv(design.design): dff_inv.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) + self.add_comment("inv: {0}".format(inv_size)) + self.inv_size = inv_size # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width. diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 629a1d67..91ccfa92 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -22,6 +22,9 @@ class dff_inv_array(design.design): dff_inv_array.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) + self.add_comment("rows: {0} cols: {1}".format(rows, columns)) + self.add_comment("inv1: {0}".format(inv1_size)) + self.inv_size = inv_size self.create_netlist() diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index ff84cfe6..67581e1a 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -14,7 +14,8 @@ class precharge_array(design.design): def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br"): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) - + self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br)) + self.columns = columns self.size = size self.bitcell_bl = bitcell_bl diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 3209377b..ebf95c95 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -14,6 +14,8 @@ class sense_amp_array(design.design): def __init__(self, name, word_size, words_per_row): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) + self.add_comment("word_size {0}".format(word_size)) + self.add_comment("words_per_row: {0}".format(words_per_row)) self.word_size = word_size self.words_per_row = words_per_row diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 9ce95c66..49293568 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -17,6 +17,8 @@ class single_level_column_mux_array(design.design): def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br"): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) + self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br)) + self.columns = columns self.word_size = word_size self.words_per_row = int(self.columns / self.word_size) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 7907247b..830c28de 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -17,7 +17,9 @@ class wordline_driver(design.design): def __init__(self, name, rows, cols): design.design.__init__(self, name) - + debug.info(1, "Creating {0}".format(self.name)) + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + self.rows = rows self.cols = cols diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 76eb9f84..3367cc00 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -15,6 +15,8 @@ class write_driver_array(design.design): def __init__(self, name, columns, word_size): design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) + self.add_comment("columns: {0}".format(columns)) + self.add_comment("word_size {0}".format(word_size)) self.columns = columns self.word_size = word_size diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 21aa7027..7b420a6b 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -58,7 +58,7 @@ class sram_factory: (obj_kwargs, obj_item) = obj # Must have the same dictionary exactly (conservative) if obj_kwargs == kwargs: - debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) + #debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) return obj_item # Use the default name if there are default arguments @@ -67,7 +67,7 @@ class sram_factory: # Create a unique name and increment the index module_name = "{0}_{1}".format(module_name, self.module_indices[module_type]) self.module_indices[module_type] += 1 - debug.info(1, "New module: type={0} name={1} kwargs={2}".format(module_type,module_name,str(kwargs))) + #debug.info(1, "New module: type={0} name={1} kwargs={2}".format(module_type,module_name,str(kwargs))) obj = mod(name=module_name,**kwargs) self.objects[module_type].append((kwargs,obj)) return obj