diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py
index 0a54a401..8776810a 100644
--- a/compiler/modules/hierarchical_decoder.py
+++ b/compiler/modules/hierarchical_decoder.py
@@ -11,6 +11,7 @@ import math
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
+from errors import drc_error
 
 
 class hierarchical_decoder(design.design):
@@ -37,18 +38,28 @@ class hierarchical_decoder(design.design):
     def find_decoder_height(self):
         b = factory.create(module_type="bitcell")
         # Old behavior
-        return (b.height, 1)
+        # return (b.height, 1)
 
         # Search for the smallest multiple that works
         cell_multiple = 1
-        while cell_multiple < 3:
+        while cell_multiple < 5:
             cell_height = cell_multiple * b.height
-            and3 = factory.create(module_type="pand3",
-                                  height=cell_height)
-            (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True)
-            if drc_errors + lvs_errors == 0:
-                return (cell_height, cell_multiple)
+            # debug.info(2,"Trying mult = {0} height={1}".format(cell_multiple, cell_height))
+            try:
+                and3 = factory.create(module_type="pand3",
+                                      height=cell_height)
+            except drc_error:
+                # debug.info(1, "Incrementing decoder height by 1 bitcell height {}".format(b.height))
+                pass
+            else:
+                (drc_errors, lvs_errors) = and3.DRC_LVS(force_check=True)
+                total_errors = drc_errors + lvs_errors
+                if total_errors == 0:
+                    debug.info(1, "Decoder height is multiple of {} bitcells.".format(cell_multiple))
+                    return (cell_height, cell_multiple)
+
             cell_multiple += 1
+            
         else:
             debug.error("Couldn't find a valid decoder height multiple.", -1)
         
diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py
index 3c2e41a2..3ec3e23e 100644
--- a/compiler/pgates/pinv.py
+++ b/compiler/pgates/pinv.py
@@ -15,6 +15,7 @@ from globals import OPTS
 from utils import round_to_grid
 import logical_effort
 from sram_factory import factory
+from errors import drc_error
 
 
 class pinv(pgate.pgate):
@@ -105,11 +106,14 @@ class pinv(pgate.pgate):
         # This is a poly-to-poly of a flipped cell
         self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space, 
                                     self.poly_extend_active + self.poly_space)
-        total_height = tx_height + min_channel + 2 * self.top_bottom_space
 
-        debug.check(self.height > total_height,
-                    "Cell height {0} too small for simple min height {1}.".format(self.height,
-                                                                                  total_height))
+        total_height = tx_height + min_channel + 2 * self.top_bottom_space
+        # debug.check(self.height > total_height,
+        #             "Cell height {0} too small for simple min height {1}.".format(self.height,
+        # total_height))
+        if total_height > self.height:
+            msg = "Cell height {0} too small for simple min height {1}.".format(self.height, total_height)
+            raise drc_error(msg)
 
         # Determine the height left to the transistors to determine
         # the number of fingers
@@ -141,12 +145,16 @@ class pinv(pgate.pgate):
         # with LVS property mismatch errors when fingers are not a grid
         # length and get rounded in the offset geometry.
         self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults)
-        debug.check(self.nmos_width >= drc("minwidth_tx"),
-                    "Cannot finger NMOS transistors to fit cell height.")
-        self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults)
-        debug.check(self.pmos_width >= drc("minwidth_tx"),
-                    "Cannot finger PMOS transistors to fit cell height.")
+        # debug.check(self.nmos_width >= drc("minwidth_tx"),
+        #            "Cannot finger NMOS transistors to fit cell height.")
+        if self.nmos_width < drc("minwidth_tx"):
+            raise drc_error("Cannot finger NMOS transistors to fit cell height.")
 
+        self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults)
+        #debug.check(self.pmos_width >= drc("minwidth_tx"),
+        #            "Cannot finger PMOS transistors to fit cell height.")
+        if self.pmos_width < drc("minwidth_tx"):
+            raise drc_error("Cannot finger NMOS transistors to fit cell height.")
         
     def add_ptx(self):
         """ Create the PMOS and NMOS transistors. """
diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py
index cc6fd0f8..3eeba41e 100644
--- a/compiler/pgates/pnand3.py
+++ b/compiler/pgates/pnand3.py
@@ -223,7 +223,7 @@ class pnand3(pgate.pgate):
                               position="center")
 
         # FIXME: constant hack
-        self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch
+        self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch
         self.route_input_gate(self.pmos1_inst,
                               self.nmos1_inst,
                               self.inputA_yoffset,
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index 357e1ce4..f07f4b29 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -108,7 +108,6 @@ class ptx(design.design):
         area_sd = 2.5 * self.poly_width * self.tx_width
         perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
         if OPTS.tech_name == "s8":
-            print("here {0}".format(self.name))
             # s8 technology is in microns
             main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
                                                                       self.mults,