diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index d42c134e..2bef2d13 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -132,40 +132,13 @@ class bitcell_array(design.design):
             # increments to the next row height
             offset.y += self.cell.height
 
-        # For every second row and column, add a via for vdd
+        # For every second row and column, add a via for gnd and vdd
         for row in range(self.row_size):
             for col in range(self.column_size):
                 inst = self.cell_inst[row,col]
-                for vdd_pin in inst.get_pins("vdd"):
-                    # Drop to M1 if needed
-                    if vdd_pin.layer == "metal1":
-                        self.add_via_center(layers=("metal1", "via1", "metal2"),
-                                            offset=vdd_pin.center(),
-                                            rotate=90)
-                    # Always drop to M2
-                    self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                        offset=vdd_pin.center())
-                    self.add_layout_pin_rect_center(text="vdd",
-                                                    layer="metal3",
-                                                    offset=vdd_pin.center())
-                                            
-                
-        # For every second row and column (+1), add a via for gnd
-        for row in range(self.row_size):
-            for col in range(self.column_size):
-                inst = self.cell_inst[row,col]
-                for gnd_pin in inst.get_pins("gnd"):
-                    # Drop to M1 if needed
-                    if gnd_pin.layer == "metal1":
-                        self.add_via_center(layers=("metal1", "via1", "metal2"),
-                                            offset=gnd_pin.center(),
-                                            rotate=90)
-                    # Always drop to M2
-                    self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                        offset=gnd_pin.center())
-                    self.add_layout_pin_rect_center(text="gnd",
-                                                    layer="metal3",
-                                                    offset=gnd_pin.center())
+                for pin_name in ["vdd", "gnd"]:
+                    for pin in inst.get_pins(pin_name):
+                        self.add_power_pin(pin_name, pin.center(), 90)
 
     def analytical_delay(self, slew, load=0):
         from tech import drc
diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
index 24dc1c03..be654d6a 100755
--- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
+#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):        
diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py
index 9de8fb77..dcb26056 100755
--- a/compiler/tests/20_psram_1bank_2mux_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_test.py
@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error")
+#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error")
 class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):